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msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 mixed signal microcontroller 1 features 23 ? low supply voltage range: 1.8 v to 3.6 v ? two configurable operational amplifiers (msp430f22x4 only) ? ultra-low power consumption ? brownout detector ? active mode: 270 a at 1 mhz, 2.2 v ? serial onboard programming, no external ? standby mode: 0.7 a programming voltage needed, programmable ? off mode (ram retention): 0.1 a code protection by security fuse ? ultra-fast wake-up from standby mode in ? bootstrap loader less than 1 s ? on-chip emulation module ? 16-bit risc architecture, 62.5-ns instruction ? family members include: cycle time ? msp430f2232 ? basic clock module configurations ? 8kb + 256b flash memory ? internal frequencies up to 16 mhz with four calibrated frequencies to 1% ? 512b ram ? internal very-low-power low-frequency ? msp430f2252 oscillator ? 16kb + 256b flash memory ? 32-khz crystal ? 512b ram ? high-frequency (hf) crystal up to 16 mhz ? msp430f2272 ? resonator ? 32kb + 256b flash memory ? external digital clock source ? 1kb ram ? external resistor ? msp430f2234 ? 16-bit timer_a with three capture/compare ? 8kb + 256b flash memory registers ? 512b ram ? 16-bit timer_b with three capture/compare ? msp430f2254 registers ? 16kb + 256b flash memory ? universal serial communication interface ? 512b ram ? enhanced uart supporting auto-baudrate ? msp430f2274 detection (lin) ? 32kb + 256b flash memory ? irda encoder and decoder ? 1kb ram ? synchronous spi ? available in a 38-pin thin shrink small-outline ? i2c ? package (tssop) (da), 40-pin qfn package ? 10-bit 200-ksps analog-to-digital (a/d) (rha) , and 49-pin ball grid array package converter with internal reference, sample- (yff) (see table 1 ) and-hold, autoscan, and data transfer ? for complete module descriptions, see the controller msp430x2xx family user's guide ( slau144 ) 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 msp430 is a trademark of texas instruments. 3 all other trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2006 ? 2012, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. description the texas instruments msp430 ? family of ultra-low-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. the architecture, combined with five low-power modes is optimized to achieve extended battery life in portable measurement applications. the device features a powerful 16-bit risc cpu, 16-bit registers, and constant generators that contribute to maximum code efficiency. the digitally controlled oscillator (dco) allows wake-up from low-power modes to active mode in less than 1 s. the msp430f22x4/msp430f22x2 series is an ultra-low-power mixed signal microcontroller with two built-in 16- bit timers, a universal serial communication interface, 10-bit a/d converter with integrated reference and data transfer controller (dtc), two general-purpose operational amplifiers in the msp430f22x4 devices, and 32 i/o pins. typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system. stand-alone radio-frequency (rf) sensor front ends are another area of application. table 1. available options packaged devices (1) (2) t a plastic 49-pin bga plastic 38-pin tssop plastic 40-pin qfn (yff) (da) (rha) msp430f2232iyff msp430f2232ida msp430f2232irha msp430f2252iyff msp430f2252ida msp430f2252irha msp430f2272iyff msp430f2272ida msp430f2272irha -40 c to 85 c msp430f2234iyff msp430f2234ida msp430f2234irha msp430f2254iyff msp430f2254ida msp430f2254irha msp430f2274iyff msp430f2274ida msp430f2274irha msp430f2232tda msp430f2232trha msp430f2252tda msp430f2252trha msp430f2272tda msp430f2272trha -40 c to 105 c msp430f2234tda msp430f2234trha msp430f2254tda msp430f2254trha msp430f2274tda msp430f2274trha (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti web site at www.ti.com . (2) package drawings, thermal data, and symbolization are available at www.ti.com/packaging . development tool support all msp430 ? microcontrollers include an embedded emulation module (eem) that allows advanced debugging and programming through easy-to-use development tools. recommended hardware options include: ? debugging and programming interface ? msp-fet430uif (usb) ? msp-fet430pif (parallel port) ? debugging and programming interface with target board ? msp-fet430u38 (da package) ? production programmer ? msp-gang430 2 copyright ? 2006 ? 2012, texas instruments incorporated
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 msp430f22x2 device pinout, da package msp430f22x4 device pinout, da package copyright ? 2006 ? 2012, texas instruments incorporated 3 1 test/sbwtck 2 dvcc 3 p2.5/r osc 4 xout/p2.7 5 xin/p2.6 6 rst/nmi/sbwtdio 7 p2.0/aclk/a0/oa0i0 8 p2.1/tainclk/smclk/a1/oa0o 9 p2.2/ta0/a2/oa0i1 10 p3.0/ucb0ste/uca0clk/a5 11 p3.1/ucb0simo/ucb0sda 12 p3.2/ucb0somi/ucb0scl 13 p3.3/ucb0clk/uca0ste 14 p4.0/tb0 15 p4.1/tb1 16 p4.2/tb2 17 p4.3/tb0/a12/oa0o 18 p4.4/tb1/a13/oa1o 19 38 p1.7/ta2/tdo/tdi 37 p1.6/ta1/tdi 36 p1.5/ta0/tms 35 p1.4/smclk/tck 34 p1.3/ta2 33 p1.2/ta1 32 p1.1/ta0 31 p1.0/taclk/adc10clk 30 p2.4/ta2/a4/vref+/veref+/oa1i0 29 p2.3/ta1/a3/vref?/veref?/oa1i1/oa1o 28 p3.7/a7/oa1i2 27 p3.6/a6/oa0i2 26 p3.5/uca0rxd/uca0somi 25 p3.4/uca0txd/uca0simo 24 23 avcc 22 avss 21 p4.7/tbclk 20 p4.6/tbouth/a15/oa1i3 dvss p4.5/tb2/a14/oa0i3 1 test/sbwtck 2 dvcc 3 p2.5/r osc 4 xout/p2.7 5 xin/p2.6 6 rst/nmi/sbwtdio 7 p2.0/aclk/a0 8 p2.1/tainclk/smclk/a1 9 p2.2/ta0/a2 10 p3.0/ucb0ste/uca0clk/a5 11 p3.1/ucb0simo/ucb0sda 12 p3.2/ucb0somi/ucb0scl 13 p3.3/ucb0clk/uca0ste 14 p4.0/tb0 15 p4.1/tb1 16 p4.2/tb2 17 p4.3/tb0/a12 18 p4.4/tb1/a13 19 38 p1.7/ta2/tdo/tdi 37 p1.6/ta1/tdi 36 p1.5/ta0/tms 35 p1.4/smclk/tck 34 p1.3/ta2 33 p1.2/ta1 32 p1.1/ta0 31 p1.0/taclk/adc10clk 30 p2.4/ta2/a4/vref+/veref+ 29 p2.3/ta1/a3/vref?/veref? 28 p3.7/a7 27 p3.6/a6 26 p3.5/uca0rxd/uca0somi 25 p3.4/uca0txd/uca0simo 24 23 avcc 22 avss 21 p4.7/tbclk 20 p4.6/tbouth/a15 dvss p4.5/tb2/a14
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com msp430f22x2 device pinout, rha package 4 copyright ? 2006 ? 2012, texas instruments incorporated 1 dvss p1.5/ta0/tms p1.0/taclk/adc10clk p1.1/ta0 p1.2/ta1 p1.3/ta2 p1.4/smclk/tck 13 p2.4/ta2/a4/vref+/veref+ p2.5/r osc dvcctest/sbwtck p1.6/ta1/tdi/tclk 23 4 5 6 7 8 10 9 12 14 15 16 17 18 19 3029 28 27 26 25 24 23 21 22 38 39 37 36 35 34 33 32 xout/p2.7 xin/p2.6 dvss rst/nmi/sbwtdio p2.0/aclk/a0 p2.1/tainclk/smclk/a1 p2.2/ta0/a2 p3.0/ucb0ste/uca0clk/a5 p3.1/ucb0simo/ucb0sda dvcc p1.7/ta2/tdo/tdi p2.3/ta1/a3/vref?/veref? p3.7/a7 p3.6/a6 p3.5/uca0rxd/uca0somi p3.4/uca0txd/uca0simo avcc avss p3.2/ucb0somi/ucb0scl p3.3/ucb0clk/uca0ste p4.0/tb0 p4.1/tb1 p4.2/tb2 p4.3/tb0/a12p4.4/tb1/a13 p4.5/tb2/a14 p4.6/tbouth/a15 p4.7/tbclk
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 msp430f22x4 device pinout, rha package copyright ? 2006 ? 2012, texas instruments incorporated 5 1 dvss p1.5/ta0/tms p1.0/taclk/adc10clk p1.1/ta0 p1.2/ta1 p1.3/ta2 p1.4/smclk/tck 13 p2.4/ta2/a4/vref+/veref+/oa1i0 p2.5/r osc dvcctest/sbwtck p1.6/ta1/tdi/tclk 23 4 5 6 7 8 10 9 12 14 15 16 17 18 19 3029 28 27 26 25 24 23 21 22 38 39 37 36 35 34 33 32 xout/p2.7 xin/p2.6 dvss rst/nmi/sbwtdio p2.0/aclk/a0/oa0i0 p2.1/tainclk/smclk/a1/oa0o p2.2/ta0/a2/oa0i1 p3.0/ucb0ste/uca0clk/a5 p3.1/ucb0simo/ucb0sda dvcc p1.7/ta2/tdo/tdi p2.3/ta1/a3/vref?/veref?/oa1i1/oa1o p3.7/a7/oa1i2 p3.6/a6/oa0i2 p3.5/uca0rxd/uca0somi p3.4/uca0txd/uca0simo avcc avss p3.2/ucb0somi/ucb0scl p3.3/ucb0clk/uca0ste p4.0/tb0 p4.1/tb1 p4.2/tb2 p4.3/tb0/a12/oa0op4.4/tb1/a13/oa1o p4.5/tb2/a14/oa0i3 p4.6/tbouth/a15/oa1i3 p4.7/tbclk
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com msp430f22x4, msp430f22x2 device pinout, yff package package dimensions the package dimensions for this yff package are shown in table 2 . see the package drawing at the end of this data sheet for more details. table 2. yff package dimensions packaged devices d e msp430f22x2 3.33 0.03 mm 3.49 0.03 mm msp430f22x4 6 copyright ? 2006 ? 2012, texas instruments incorporated a1 a2 a4 a3 a5 a6 a7 top view b1 b2 b4 b3 b5 b6 b7 c1 c2 c4 c3 c5 c6 c7 d1 d2 d4 d3 d5 d6 d7 e1 e2 e4 e3 e5 e6 e7 f1 f2 f4 f3 f5 f6 f7 g1 g2 g4 g3 g5 g6 g7
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 msp430f22x2 functional block diagram msp430f22x4 functional block diagram copyright ? 2006 ? 2012, texas instruments incorporated 7 basic clock system+ ram 1kb 512b 512b brownout protection rst/nmi vcc vss mclk smclk watchdog wdt+ 15/16?bit timer_a3 3 cc registers 16mhz cpu incl. 16 registers emulation (2bp) xout jtag interface flash 32kb 16kb 8kb aclk xin mdb mab spy?bi wire timer_b3 3 cc registers, shadow reg usci_a0: uart/lin, irda, spi usci_b0: spi, i2c oa0, oa1 2 op amps adc10 10?bit 12 channels, autoscan, dtc ports p1/p2 2x8 i/o interrupt capability, pull?up/down resistors ports p3/p4 2x8 i/o pull?up/down resistors p1.x/p2.x 2x8 p3.x/p4.x 2x8 basic clock system+ ram 1kb 512b 512b brownout protection rst/nmi vcc vss mclk smclk watchdog wdt+ 15/16?bit timer_a3 3 cc registers 16mhz cpu incl. 16 registers emulation (2bp) xout jtag interface flash 32kb 16kb 8kb aclk xin mdb mab spy?bi wire timer_b3 3 cc registers, shadow reg usci_a0: uart/lin, irda, spi usci_b0: spi, i2c adc10 10?bit 12 channels, autoscan, dtc ports p1/p2 2x8 i/o interrupt capability, pull?up/down resistors ports p3/p4 2x8 i/o pull?up/down resistors p1.x/p2.x 2x8 p3.x/p4.x 2x8
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com table 3. terminal functions, msp430f22x2 terminal no. i/o description name yff da rha general-purpose digital i/o pin p1.0/taclk/adc10clk f2 31 29 i/o timer_a, clock signal taclk input adc10, conversion clock general-purpose digital i/o pin p1.1/ta0 g2 32 30 i/o timer_a, capture: cci0a input, compare: out0 output bsl transmit general-purpose digital i/o pin p1.2/ta1 e2 33 31 i/o timer_a, capture: cci1a input, compare: out1 output general-purpose digital i/o pin p1.3/ta2 g1 34 32 i/o timer_a, capture: cci2a input, compare: out2 output general-purpose digital i/o pin p1.4/smclk/tck f1 35 33 i/o smclk signal output test clock input for device programming and test general-purpose digital i/o pin p1.5/ta0/tms e1 36 34 i/o timer_a, compare: out0 output test mode select input for device programming and test general-purpose digital i/o pin p1.6/ta1/tdi/tclk e3 37 35 i/o timer_a, compare: out1 output test data input or test clock input for programming and test general-purpose digital i/o pin p1.7/ta2/tdo/tdi (1) d2 38 36 i/o timer_a, compare: out2 output test data output or test data input for programming and test general-purpose digital i/o pin p2.0/aclk/a0 a4 8 6 i/o aclk output adc10, analog input a0 general-purpose digital i/o pin timer_a, clock signal at inclk p2.1/tainclk/smclk/a1 b4 9 7 i/o smclk signal output adc10, analog input a1 general-purpose digital i/o pin p2.2/ta0/a2 a5 10 8 i/o timer_a, capture: cci0b input/bsl receive, compare: out0 output adc10, analog input a2 general-purpose digital i/o pin timer_a, capture cci1b input, compare: out1 output p2.3/ta1/a3/v ref- / v eref- f3 29 27 i/o adc10, analog input a3 negative reference voltage input general-purpose digital i/o pin timer_a, compare: out2 output p2.4/ta2/a4/v ref+ / v eref+ g3 30 28 i/o adc10, analog input a4 positive reference voltage output or input general-purpose digital i/o pin p2.5/r osc c2 3 40 i/o input for external dco resistor to define dco frequency input terminal of crystal oscillator xin/p2.6 a2 6 3 i/o general-purpose digital i/o pin (1) tdo or tdi is selected via jtag instruction. 8 copyright ? 2006 ? 2012, texas instruments incorporated
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 table 3. terminal functions, msp430f22x2 (continued) terminal no. i/o description name yff da rha output terminal of crystal oscillator xout/p2.7 a1 5 2 i/o general-purpose digital i/o pin (2) general-purpose digital i/o pin usci_b0 slave transmit enable p3.0/ucb0ste/uca0clk/ b5 11 9 i/o a5 usci_a0 clock input/output adc10, analog input a5 general-purpose digital i/o pin p3.1/ucb0simo/ a6 12 10 i/o usci_b0 spi mode: slave in/master out ucb0sda usci_b0 i2c mode: sda i2c data general-purpose digital i/o pin p3.2/ucb0somi/ucb0scl a7 13 11 i/o usci_b0 spi mode: slave out/master in usci_b0 i2c mode: scl i2c clock general-purpose digital i/o pin p3.3/ucb0clk/uca0ste b6 14 12 i/o usci_b0 clock input/output usci_a0 slave transmit enable general-purpose digital i/o pin p3.4/uca0txd/ g6 25 23 i/o usci_a0 uart mode: transmit data output uca0simo usci_a0 spi mode: slave in/master out general-purpose digital i/o pin p3.5/uca0rxd/ g5 26 24 i/o usci_a0 uart mode: receive data input uca0somi usci_a0 spi mode: slave out/master in general-purpose digital i/o pin p3.6/a6 f4 27 25 i/o adc10 analog input a6 general-purpose digital i/o pin p3.7/a7 g4 28 26 i/o adc10 analog input a7 general-purpose digital i/o pin p4.0/tb0 d6 17 15 i/o timer_b, capture: cci0a input, compare: out0 output general-purpose digital i/o pin p4.1/tb1 d7 18 16 i/o timer_b, capture: cci1a input, compare: out1 output general-purpose digital i/o pin p4.2/tb2 e6 19 17 i/o timer_b, capture: cci2a input, compare: out2 output general-purpose digital i/o pin p4.3/tb0/a12 e7 20 18 i/o timer_b, capture: cci0b input, compare: out0 output adc10 analog input a12 general-purpose digital i/o pin p4.4/tb1/a13 f7 21 19 i/o timer_b, capture: cci1b input, compare: out1 output adc10 analog input a13 general-purpose digital i/o pin p4.5/tb2/a14 f6 22 20 i/o timer_b, compare: out2 output adc10 analog input a14 general-purpose digital i/o pin p4.6/tbouth/a15 g7 23 21 i/o timer_b, switch all tb0 to tb3 outputs to high impedance adc10 analog input a15 (2) if xout/p2.7 is used as an input, excess current flows until p2sel.7 is cleared. this is due to the oscillator output driver connection to this pad after reset. copyright ? 2006 ? 2012, texas instruments incorporated 9
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com table 3. terminal functions, msp430f22x2 (continued) terminal no. i/o description name yff da rha general-purpose digital i/o pin p4.7/tbclk f5 24 22 i/o timer_b, clock signal tbclk input reset or nonmaskable interrupt input rst/nmi/sbwtdio b3 7 5 i spy-bi-wire test data input/output during programming and test selects test mode for jtag pins on port 1. the device protection fuse is connected to test. test/sbwtck d1 1 37 i spy-bi-wire test clock input during programming and test c1, d3, dv cc 2 38, 39 digital supply voltage d4, e4, e5 c6, av cc c7, 16 14 analog supply voltage d5 a3, b1, dv ss b2, 4 1, 4 digital ground reference c3, c4 b7, av ss 15 13 analog ground reference c5 qfn pad na na pad na qfn package pad; connection to dv ss recommended. 10 copyright ? 2006 ? 2012, texas instruments incorporated
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 table 4. terminal functions, msp430f22x4 terminal no. i/o description name yff da rha general-purpose digital i/o pin p1.0/taclk/adc10clk f2 31 29 i/o timer_a, clock signal taclk input adc10, conversion clock general-purpose digital i/o pin p1.1/ta0 g2 32 30 i/o timer_a, capture: cci0a input, compare: out0 output bsl transmit general-purpose digital i/o pin p1.2/ta1 e2 33 31 i/o timer_a, capture: cci1a input, compare: out1 output general-purpose digital i/o pin p1.3/ta2 g1 34 32 i/o timer_a, capture: cci2a input, compare: out2 output general-purpose digital i/o pin p1.4/smclk/tck f1 35 33 i/o smclk signal output test clock input for device programming and test general-purpose digital i/o pin p1.5/ta0/tms e1 36 34 i/o timer_a, compare: out0 output test mode select input for device programming and test general-purpose digital i/o pin p1.6/ta1/tdi/tclk e3 37 35 i/o timer_a, compare: out1 output test data input or test clock input for programming and test general-purpose digital i/o pin p1.7/ta2/tdo/tdi (1) d2 38 36 i/o timer_a, compare: out2 output test data output or test data input for programming and test general-purpose digital i/o pin aclk output p2.0/aclk/a0/oa0i0 a4 8 6 i/o adc10, analog input a0 oa0, analog input io general-purpose digital i/o pin timer_a, clock signal at inclk p2.1/tainclk/smclk/ b4 9 7 i/o smclk signal output a1/oa0o adc10, analog input a1 oa0, analog output general-purpose digital i/o pin timer_a, capture: cci0b input/bsl receive, compare: out0 output p2.2/ta0/a2/oa0i1 a5 10 8 i/o adc10, analog input a2 oa0, analog input i1 general-purpose digital i/o pin timer_a, capture cci1b input, compare: out1 output adc10, analog input a3 p2.3/ta1/a3/ v ref- /v eref- / f3 29 27 i/o oa1i1/oa1o negative reference voltage input oa1, analog input i1 oa1, analog output (1) tdo or tdi is selected via jtag instruction. copyright ? 2006 ? 2012, texas instruments incorporated 11
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com table 4. terminal functions, msp430f22x4 (continued) terminal no. i/o description name yff da rha general-purpose digital i/o pin timer_a, compare: out2 output p2.4/ta2/a4/ g3 30 28 i/o adc10, analog input a4 v ref+ /v eref+ /oa1i0 positive reference voltage output or input oa1, analog input i/o general-purpose digital i/o pin p2.5/r osc c2 3 40 i/o input for external dco resistor to define dco frequency input terminal of crystal oscillator xin/p2.6 a2 6 3 i/o general-purpose digital i/o pin output terminal of crystal oscillator xout/p2.7 a1 5 2 i/o general-purpose digital i/o pin (2) general-purpose digital i/o pin usci_b0 slave transmit enable p3.0/ucb0ste/uca0clk/ b5 11 9 i/o a5 usci_a0 clock input/output adc10, analog input a5 general-purpose digital i/o pin p3.1/ucb0simo/ a6 12 10 i/o usci_b0 spi mode: slave in/master out ucb0sda usci_b0 i2c mode: sda i2c data general-purpose digital i/o pin p3.2/ucb0somi/ucb0scl a7 13 11 i/o usci_b0 spi mode: slave out/master in usci_b0 i2c mode: scl i2c clock general-purpose digital i/o pin p3.3/ucb0clk/uca0ste b6 14 12 i/o usci_b0 clock input/output usci_a0 slave transmit enable general-purpose digital i/o pin p3.4/uca0txd/ g6 25 23 i/o usci_a0 uart mode: transmit data output uca0simo usci_a0 spi mode: slave in/master out general-purpose digital i/o pin p3.5/uca0rxd/ g5 26 24 i/o usci_a0 uart mode: receive data input uca0somi usci_a0 spi mode: slave out/master in general-purpose digital i/o pin p3.6/a6/oa0i2 f4 27 25 i/o adc10 analog input a6 oa0 analog input i2 general-purpose digital i/o pin p3.7/a7/oa1i2 g4 28 26 i/o adc10 analog input a7 oa1 analog input i2 general-purpose digital i/o pin p4.0/tb0 d6 17 15 i/o timer_b, capture: cci0a input, compare: out0 output general-purpose digital i/o pin p4.1/tb1 d7 18 16 i/o timer_b, capture: cci1a input, compare: out1 output general-purpose digital i/o pin p4.2/tb2 e6 19 17 i/o timer_b, capture: cci2a input, compare: out2 output (2) if xout/p2.7 is used as an input, excess current flows until p2sel.7 is cleared. this is due to the oscillator output driver connection to this pad after reset. 12 copyright ? 2006 ? 2012, texas instruments incorporated
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 table 4. terminal functions, msp430f22x4 (continued) terminal no. i/o description name yff da rha general-purpose digital i/o pin timer_b, capture: cci0b input, compare: out0 output p4.3/tb0/a12/oa0o e7 20 18 i/o adc10 analog input a12 oa0 analog output general-purpose digital i/o pin timer_b, capture: cci1b input, compare: out1 output p4.4/tb1/a13/oa1o f7 21 19 i/o adc10 analog input a13 oa1 analog output general-purpose digital i/o pin timer_b, compare: out2 output p4.5/tb2/a14/oa0i3 f6 22 20 i/o adc10 analog input a14 oa0 analog input i3 general-purpose digital i/o pin timer_b, switch all tb0 to tb3 outputs to high impedance p4.6/tbouth/a15/oa1i3 g7 23 21 i/o adc10 analog input a15 oa1 analog input i3 general-purpose digital i/o pin p4.7/tbclk f5 24 22 i/o timer_b, clock signal tbclk input reset or nonmaskable interrupt input rst/nmi/sbwtdio b3 7 5 i spy-bi-wire test data input/output during programming and test selects test mode for jtag pins on port 1. the device protection fuse is connected to test. test/sbwtck d1 1 37 i spy-bi-wire test clock input during programming and test c1, d3, dv cc 2 38, 39 digital supply voltage d4, e4, e5 c6, av cc c7, 16 14 analog supply voltage d5 a3, b1, dv ss b2, 4 1, 4 digital ground reference c3, c4 b7, av ss 15 13 analog ground reference c5 qfn pad na na pad na qfn package pad; connection to dv ss recommended. copyright ? 2006 ? 2012, texas instruments incorporated 13
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com short-form description cpu the msp430 ? cpu has a 16-bit risc architecture that is highly transparent to the application. all operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. the cpu is integrated with 16 registers that provide reduced instruction execution time. the register-to- register operation execution time is one cycle of the cpu clock. four of the registers, r0 to r3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. the remaining registers are general-purpose registers. peripherals are connected to the cpu using data, address, and control buses and can be handled with all instructions. instruction set the instruction set consists of 51 instructions with three formats and seven address modes. each instruction can operate on word and byte data. table 5 shows examples of the three types of instruction formats; table 6 shows the address modes. table 5. instruction word formats instruction format example operation dual operands, source-destination add r4,r5 r4 + r5 r5 single operands, destination only call r8 pc (tos), r8 pc relative jump, unconditional/conditional jne jump-on-equal bit = 0 table 6. address mode descriptions address mode s (1) d (2) syntax example operation register ? ? mov rs,rd mov r10,r11 r10 r11 indexed ? ? mov x(rn),y(rm) mov 2(r5),6(r6) m(2+r5) m(6+r6) symbolic (pc relative) ? ? mov ede,toni m(ede) m(toni) absolute ? ? mov & mem, & tcdat m(mem) m(tcdat) indirect ? mov @rn,y(rm) mov @r10,tab(r6) m(r10) m(tab+r6) m(r10) r11 indirect autoincrement ? mov @rn+,rm mov @r10+,r11 r10 + 2 r10 immediate ? mov #x,toni mov #45,toni #45 m(toni) (1) s = source (2) d = destination 14 copyright ? 2006 ? 2012, texas instruments incorporated general-purpose register program counter stack pointer status register constant generator general-purpose register general-purpose register general-purpose register pc/r0sp/r1 sr/cg1/r2 cg2/r3 r4 r5 r12 r13 general-purpose register general-purpose register r6 r7 general-purpose register general-purpose register r8 r9 general-purpose register general-purpose register r10 r11 general-purpose register general-purpose register r14 r15
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 operating modes the msp430 microcontrollers have one active mode and five software-selectable low-power modes of operation. an interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. the following six operating modes can be configured by software: ? active mode (am) ? all clocks are active. ? low-power mode 0 (lpm0) ? cpu is disabled. ? aclk and smclk remain active. mclk is disabled. ? low-power mode 1 (lpm1) ? cpu is disabled aclk and smclk remain active. mclk is disabled. ? dco dc-generator is disabled if dco not used in active mode. ? low-power mode 2 (lpm2) ? cpu is disabled. ? mclk and smclk are disabled. ? dco dc-generator remains enabled. ? aclk remains active. ? low-power mode 3 (lpm3) ? cpu is disabled. ? mclk and smclk are disabled. ? dco dc-generator is disabled. ? aclk remains active. ? low-power mode 4 (lpm4) ? cpu is disabled. ? aclk is disabled. ? mclk and smclk are disabled. ? dco dc-generator is disabled. ? crystal oscillator is stopped. copyright ? 2006 ? 2012, texas instruments incorporated 15
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com interrupt vector addresses the interrupt vectors and the power-up starting address are located in the address range of 0ffffh to 0ffc0h. the vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. if the reset vector (located at address 0fffeh) contains 0ffffh (for example, if flash is not programmed), the cpu goes into lpm4 immediately after power up. table 7. interrupt vector addresses system interrupt source interrupt flag word address priority interrupt power-up porifg external reset rstifg watchdog reset 0fffeh 31, highest wdtifg flash key violation keyv (2) pc out-of-range (1) nmi nmiifg (non)-maskable, oscillator fault ofifg (non)-maskable, 0fffch 30 flash memory access violation accvifg (2) (3) (non)-maskable timer_b3 tbccr0 ccifg (4) maskable 0fffah 29 tbccr1 and tbccr2 ccifgs, timer_b3 maskable 0fff8h 28 tbifg (2) (4) 0fff6h 27 watchdog timer wdtifg maskable 0fff4h 26 timer_a3 taccr0 ccifg (see note 3) maskable 0fff2h 25 taccr1 ccifg timer_a3 taccr2 ccifg maskable 0fff0h 24 taifg (2) (4) usci_a0/usci_b0 receive uca0rxifg, ucb0rxifg (2) maskable 0ffeeh 23 usci_a0/usci_b0 transmit uca0txifg, ucb0txifg (2) maskable 0ffech 22 adc10 adc10ifg (4) maskable 0ffeah 21 0ffe8h 20 i/o port p2 p2ifg.0 to p2ifg.7 (2) (4) maskable 0ffe6h 19 (eight flags) i/o port p1 p1ifg.0 to p1ifg.7 (2) (4) maskable 0ffe4h 18 (eight flags) 0ffe2h 17 0ffe0h 16 (5) 0ffdeh 15 (6) 0ffdch to 0ffc0h 14 to 0, lowest (1) a reset is generated if the cpu tries to fetch instructions from within the module register memory address range (0h to 01ffh) or from within unused address range. (2) multiple source flags (3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event. (4) interrupt flags are located in the module. (5) this location is used as bootstrap loader security key (bslskey). a 0aa55h at this location disables the bsl completely. a zero (0h) disables the erasure of the flash if an invalid password is supplied. (6) the interrupt vectors at addresses 0ffdch to 0ffc0h are not used in this device and can be used for regular program code if necessary. 16 copyright ? 2006 ? 2012, texas instruments incorporated
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 special function registers most interrupt and module enable bits are collected into the lowest address space. special function register bits not allocated to a functional purpose are not physically present in the device. simple software access is provided with this arrangement. legend rw bit can be read and written. rw-0, 1 bit can be read and written. it is reset or set by puc. rw-(0), (1) bit can be read and written. it is reset or set by por. sfr bit is not present in device. table 8. interrupt enable 1 address 7 6 5 4 3 2 1 0 00h accvie nmiie ofie wdtie rw-0 rw-0 rw-0 rw-0 wdtie watchdog timer interrupt enable. inactive if watchdog mode is selected. active if watchdog timer is configured in interval timer mode. ofie oscillator fault interrupt enable nmiie (non)maskable interrupt enable accvie flash access violation interrupt enable table 9. interrupt enable 2 address 7 6 5 4 3 2 1 0 01h ucb0txie ucb0rxie uca0txie uca0rxie rw-0 rw-0 rw-0 rw-0 uca0rxie usci_a0 receive-interrupt enable uca0txie usci_a0 transmit-interrupt enable ucb0rxie usci_b0 receive-interrupt enable ucb0txie usci_b0 transmit-interrupt enable table 10. interrupt flag register 1 address 7 6 5 4 3 2 1 0 02h nmiifg rstifg porifg ofifg wdtifg rw-0 rw-(0) rw-(1) rw-1 rw-(0) wdtifg set on watchdog timer overflow (in watchdog mode) or security key violation. reset on v cc power-up or a reset condition at rst/nmi pin in reset mode. ofifg flag set on oscillator fault rstifg external reset interrupt flag. set on a reset condition at rst/nmi pin in reset mode. reset on v cc power up. porifg power-on reset interrupt flag. set on v cc power up. nmiifg set via rst/nmi pin table 11. interrupt flag register 2 address 7 6 5 4 3 2 1 0 03h ucb0txifg ucb0rxifg uca0txifg uca0rxifg rw-1 rw-0 rw-1 rw-0 uca0rxifg usci_a0 receive-interrupt flag uca0txifg usci_a0 transmit-interrupt flag ucb0rxifg usci_b0 receive-interrupt flag ucb0txifg usci_b0 transmit-interrupt flag copyright ? 2006 ? 2012, texas instruments incorporated 17
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com memory organization table 12. memory organization msp430f223x msp430f225x msp430f227x memory size 8kb flash 16kb flash 32kb flash main: interrupt vector flash 0ffffh-0ffc0h 0ffffh-0ffc0h 0ffffh-0ffc0h main: code memory flash 0ffffh-0e000h 0ffffh-0c000h 0ffffh-08000h size 256 byte 256 byte 256 byte information memory flash 010ffh-01000h 010ffh-01000h 010ffh-01000h size 1kb 1kb 1kb boot memory rom 0fffh-0c00h 0fffh-0c00h 0fffh-0c00h 512 byte 512 byte 1kb ram size 03ffh-0200h 03ffh-0200h 05ffh-0200h 16-bit 01ffh-0100h 01ffh-0100h 01ffh-0100h peripherals 8-bit 0ffh-010h 0ffh-010h 0ffh-010h 8-bit sfr 0fh-00h 0fh-00h 0fh-00h bootstrap loader (bsl) the msp430 bootstrap loader (bsl) enables users to program the flash memory or ram using a uart serial interface. access to the msp430 memory via the bsl is protected by user-defined password. for complete description of the features of the bsl and its implementation, see the msp430 programming via the bootstrap loader user ? s guide ( slau319 ). table 13. bsl function pins bsl function da package pins rha package pins yff package pins data transmit 32 - p1.1 30 - p1.1 g3 - p1.1 data receive 10 - p2.2 8 - p2.2 a5 - p2.2 flash memory the flash memory can be programmed via the jtag port, the bootstrap loader, or in-system by the cpu. the cpu can perform single-byte and single-word writes to the flash memory. features of the flash memory include: ? flash memory has n segments of main memory and four segments of information memory (a to d) of 64 bytes each. each segment in main memory is 512 bytes in size. ? segments 0 to n may be erased in one step, or each segment may be individually erased. ? segments a to d can be erased individually, or as a group with segments 0 to n. segments a to d are also called information memory . ? segment a contains calibration data. after reset, segment a is protected against programming and erasing. it can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is required. 18 copyright ? 2006 ? 2012, texas instruments incorporated
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 peripherals peripherals are connected to the cpu through data, address, and control buses and can be handled using all instructions. for complete module descriptions, see the msp430x2xx family user's guide ( slau144 ). oscillator and system clock the clock system is supported by the basic clock module that includes support for a 32768-hz watch crystal oscillator, an internal very-low-power low-frequency oscillator, an internal digitally-controlled oscillator (dco), and a high-frequency crystal oscillator. the basic clock module is designed to meet the requirements of both low system cost and low power consumption. the internal dco provides a fast turn-on clock source and stabilizes in less than 1 s. the basic clock module provides the following clock signals: ? auxiliary clock (aclk), sourced from a 32768-hz watch crystal, a high-frequency crystal, or the internal very- low-power lf oscillator. ? main clock (mclk), the system clock used by the cpu. ? sub-main clock (smclk), the sub-system clock used by the peripheral modules. table 14. dco calibration data (provided from factory in flash information memory segment a) dco frequency calibration register size address calbc1_1mhz byte 010ffh 1 mhz caldco_1mhz byte 010feh calbc1_8mhz byte 010fdh 8 mhz caldco_8mhz byte 010fch calbc1_12mhz byte 010fbh 12 mhz caldco_12mhz byte 010fah calbc1_16mhz byte 010f9h 16 mhz caldco_16mhz byte 010f8h brownout the brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. digital i/o there are four 8-bit i/o ports implemented ? ports p1, p2, p3, and p4: ? all individual i/o bits are independently programmable. ? any combination of input, output, and interrupt condition is possible. ? edge-selectable interrupt input capability for all eight bits of port p1 and p2. ? read/write access to port-control registers is supported by all instructions. ? each i/o has an individually programmable pullup/pulldown resistor. because there are only three i/o pins implemented from port p2, bits [5:1] of all port p2 registers read as 0, and write data is ignored. watchdog timer (wdt+) the primary function of the wdt+ module is to perform a controlled system restart after a software problem occurs. if the selected time interval expires, a system reset is generated. if the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals. copyright ? 2006 ? 2012, texas instruments incorporated 19
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com timer_a3 timer_a3 is a 16-bit timer/counter with three capture/compare registers. timer_a3 can support multiple capture/compares, pwm outputs, and interval timing. timer_a3 also has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. table 15. timer_a3 signal connections input pin number device module module output pin number module input input output block da rha yff da rha yff signal name signal 31 - p1.0 29 - p1.0 f2 - p1.0 taclk taclk timer na aclk aclk smclk smclk 9 - p2.1 7 - p2.1 b4 - p2.1 tainclk inclk 32 - p1.1 30 - p1.1 g2 - p1.1 ta0 cci0a ccr0 ta0 32 - p1.1 30 - p1.1 g2 - p1.1 10 - p2.2 8 - p2.2 a5 - p2.2 ta0 cci0b 10 - p2.2 8 - p2.2 a5 - p2.2 v ss gnd 36 - p1.5 34 - p1.5 e1 - p1.5 v cc v cc 33 - p1.2 31 - p1.2 e2 - p1.2 ta1 cci1a ccr1 ta1 33 - p1.2 31 - p1.2 e2 - p1.2 29 - p2.3 27 - p2.3 f3 - p2.3 ta1 cci1b 29 - p2.3 27 - p2.3 f3 - p2.3 v ss gnd 37 - p1.6 35 - p1.6 e3 - p1.6 v cc v cc 34 - p1.3 32 - p1.3 g1 - p1.3 ta2 cci2a ccr2 ta2 34 - p1.3 32 - p1.3 g1 - p1.3 aclk cci2b 30 - p2.4 28 - p2.4 g3 - p2.4 (internal) v ss gnd 38 - p1.7 36 - p1.7 d2 - p1.7 v cc v cc 20 copyright ? 2006 ? 2012, texas instruments incorporated
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 timer_b3 timer_b3 is a 16-bit timer/counter with three capture/compare registers. timer_b3 can support multiple capture/compares, pwm outputs, and interval timing. timer_b3 also has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. table 16. timer_b3 signal connections input pin number device module module output pin number module input input output block da rha yff da rha yff signal name signal 24 - p4.7 22 - p4.7 f5 - p4.7 tbclk tbclk timer na aclk aclk smclk smclk 24 - p4.7 22 - p4.7 f5 - p4.7 tbclk inclk 17 - p4.0 15 - p4.0 d6 - p4.0 tb0 cci0a ccr0 tb0 17 - p4.0 15 - p4.0 d6 - p4.0 20 - p4.3 18 - p4.3 e7 - p4.3 tb0 cci0b 20 - p4.3 18 - p4.3 e7 - p4.3 v ss gnd v cc v cc 18 - p4.1 16 - p4.1 d7 - p4.1 tb1 cci1a ccr1 tb1 18 - p4.1 16 - p4.1 d7 - p4.1 21 - p4.4 19 - p4.4 f7 - p4.4 tb1 cci1b 21 - p4.4 19 - p4.4 f7 - p4.4 v ss gnd v cc v cc 19 - p4.2 17 - p4.2 e6 - p4.2 tb2 cci2a ccr2 tb2 19 - p4.2 17 - p4.2 e6 - p4.2 aclk cci2b 22 - p4.5 20 - p4.5 f6 - p4.5 (internal) v ss gnd v cc v cc universal serial communications interface (usci) the usci module is used for serial data communication. the usci module supports synchronous communication protocols like spi (3 or 4 pin), i2c and asynchronous communication protocols such as uart, enhanced uart with automatic baudrate detection (lin), and irda. usci_a0 provides support for spi (3 or 4 pin), uart, enhanced uart, and irda. usci_b0 provides support for spi (3 or 4 pin) and i2c. adc10 the adc10 module supports fast, 10-bit analog-to-digital conversions. the module implements a 10-bit sar core, sample select control, reference generator and data transfer controller, or dtc, for automatic conversion result handling allowing adc samples to be converted and stored without any cpu intervention. copyright ? 2006 ? 2012, texas instruments incorporated 21
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com operational amplifier (oa) (msp430f22x4 only) the msp430f22x4 has two configurable low-current general-purpose operational amplifiers. each oa input and output terminal is software-selectable and offer a flexible choice of connections for various applications. the oa op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion. table 17. oa0 signal connections analog input pin number device input signal module input name da rha yff 8 - a0 6 - a0 b4 - a0 oa0i0 oaxi0 10 - a2 8 - a2 b5 - a2 oa0i1 oa0i1 10 - a2 8 - a2 b5 - a2 oa0i1 oaxi1 27 - a6 25 - a6 f4 - a6 oa0i2 oaxia 22 - a14 20 - a14 f6 - a14 oa0i3 oaxib table 18. oa1 signal connections analog input pin number device input signal module input name da rha yff 30 - a4 28 - a4 g3 - a4 oa1i0 oaxi0 10 - a2 8 - a2 b5 - a2 oa0i1 oa0i1 29 - a3 27 - a3 f3 - a3 oa1i1 oaxi1 28 - a7 26 - a7 g4 - a7 oa1i2 oaxia 23 - a15 21 - a15 g7 - a15 oa1i3 oaxib 22 copyright ? 2006 ? 2012, texas instruments incorporated
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 peripheral file map table 19. peripherals with word access module register name short name address offset adc10 adc data transfer start address adc10sa 1bch adc memory adc10mem 1b4h adc control register 1 adc10ctl1 1b2h adc control register 0 adc10ctl0 1b0h adc analog enable 0 adc10ae0 04ah adc analog enable 1 adc10ae1 04bh adc data transfer control register 1 adc10dtc1 049h adc data transfer control register 0 adc10dtc0 048h timer_b capture/compare register tbccr2 0196h capture/compare register tbccr1 0194h capture/compare register tbccr0 0192h timer_b register tbr 0190h capture/compare control tbcctl2 0186h capture/compare control tbcctl1 0184h capture/compare control tbcctl0 0182h timer_b control tbctl 0180h timer_b interrupt vector tbiv 011eh timer_a capture/compare register taccr2 0176h capture/compare register taccr1 0174h capture/compare register taccr0 0172h timer_a register tar 0170h capture/compare control tacctl2 0166h capture/compare control tacctl1 0164h capture/compare control tacctl0 0162h timer_a control tactl 0160h timer_a interrupt vector taiv 012eh flash memory flash control 3 fctl3 012ch flash control 2 fctl2 012ah flash control 1 fctl1 0128h watchdog timer+ watchdog/timer control wdtctl 0120h copyright ? 2006 ? 2012, texas instruments incorporated 23
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com table 20. peripherals with byte access module register name short name address offset oa1 (msp430f22x4 only) operational amplifier 1 control register 1 oa1ctl1 0c3h operational amplifier 1 control register 1 oa1ctl0 0c2h oa0 (msp430f22x4 only) operational amplifier 0 control register 1 oa0ctl1 0c1h operational amplifier 0 control register 1 oa0ctl0 0c0h usci_b0 usci_b0 transmit buffer ucb0txbuf 06fh usci_b0 receive buffer ucb0rxbuf 06eh usci_b0 status ucb0stat 06dh usci_b0 bit rate control 1 ucb0br1 06bh usci_b0 bit rate control 0 ucb0br0 06ah usci_b0 control 1 ucb0ctl1 069h usci_b0 control 0 ucb0ctl0 068h usci_b0 i2c slave address ucb0sa 011ah usci_b0 i2c own address ucb0oa 0118h usci_a0 usci_a0 transmit buffer uca0txbuf 067h usci_a0 receive buffer uca0rxbuf 066h usci_a0 status uca0stat 065h usci_a0 modulation control uca0mctl 064h usci_a0 baud rate control 1 uca0br1 063h usci_a0 baud rate control 0 uca0br0 062h usci_a0 control 1 uca0ctl1 061h usci_a0 control 0 uca0ctl0 060h usci_a0 irda receive control uca0irrctl 05fh usci_a0 irda transmit control uca0irtctl 05eh usci_a0 auto baud rate control uca0abctl 05dh basic clock system+ basic clock system control 3 bcsctl3 053h basic clock system control 2 bcsctl2 058h basic clock system control 1 bcsctl1 057h dco clock frequency control dcoctl 056h port p4 port p4 resistor enable p4ren 011h port p4 selection p4sel 01fh port p4 direction p4dir 01eh port p4 output p4out 01dh port p4 input p4in 01ch port p3 port p3 resistor enable p3ren 010h port p3 selection p3sel 01bh port p3 direction p3dir 01ah port p3 output p3out 019h port p3 input p3in 018h port p2 port p2 resistor enable p2ren 02fh port p2 selection p2sel 02eh port p2 interrupt enable p2ie 02dh port p2 interrupt edge select p2ies 02ch port p2 interrupt flag p2ifg 02bh port p2 direction p2dir 02ah port p2 output p2out 029h port p2 input p2in 028h 24 copyright ? 2006 ? 2012, texas instruments incorporated
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 table 20. peripherals with byte access (continued) module register name short name address offset port p1 port p1 resistor enable p1ren 027h port p1 selection p1sel 026h port p1 interrupt enable p1ie 025h port p1 interrupt edge select p1ies 024h port p1 interrupt flag p1ifg 023h port p1 direction p1dir 022h port p1 output p1out 021h port p1 input p1in 020h special function sfr interrupt flag 2 ifg2 003h sfr interrupt flag 1 ifg1 002h sfr interrupt enable 2 ie2 001h sfr interrupt enable 1 ie1 000h copyright ? 2006 ? 2012, texas instruments incorporated 25
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com absolute maximum ratings (1) voltage applied at v cc to v ss -0.3 v to 4.1 v voltage applied to any pin (2) -0.3 v to v cc + 0.3 v diode current at any device terminal 2 ma unprogrammed device -55 c to 150 c storage temperature, t stg (3) programmed device -55 c to 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltages referenced to v ss . the jtag fuse-blow voltage, v fb , is allowed to exceed the absolute maximum rating. the voltage is applied to the test pin when blowing the jtag fuse. (3) higher temperature may be applied during board soldering process according to the current jedec j-std-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. recommended operating conditions (1) (2) min nom max unit during program 1.8 3.6 v execution v cc supply voltage av cc = dv cc = v cc during program/erase 2.2 3.6 v flash memory v ss supply voltage av ss = dv ss = v ss 0 v i version -40 85 t a operating free-air temperature c t version -40 105 v cc = 1.8 v, duty cycle = 50% 10% dc 4.15 processor frequency f system (maximum mclk frequency) (1) (2) v cc = 2.7 v, duty cycle = 50% 10% dc 12 mhz (see figure 1 ) v cc 3.3 v, duty cycle = 50% 10% dc 16 (1) the msp430 cpu is clocked directly with mclk. both the high and low phase of mclk must not exceed the pulse width of the specified maximum frequency. (2) modules might have a different maximum input clock specification. see the specification of the respective module in this data sheet. note: minimum processor frequency is defined by system clock. flash program or erase operations require a minimum v cc of 2.2 v. figure 1. operating area 26 copyright ? 2006 ? 2012, texas instruments incorporated 4.15 mhz 12 mhz 16 mhz 1.8 v 2.2 v 2.7 v 3.3 v 3.6 v supply voltage ?v system frequency ?mhz supply voltage range, during flash memory programming supply voltage range, during program execution legend : 7.5 mhz
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 active mode supply current (into dv cc + av cc ) excluding external current (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions t a v cc min typ max unit f dco = f mclk = f smclk = 1 mhz, 2.2 v 270 390 f aclk = 32768 hz, program executes in flash, active mode (am) i am,1mhz bcsctl1 = calbc1_1mhz, a current (1 mhz) 3 v 390 550 dcoctl = caldco_1mhz, cpuoff = 0, scg0 = 0, scg1 = 0, oscoff = 0 f dco = f mclk = f smclk = 1 mhz, 2.2 v 240 f aclk = 32768 hz, program executes in ram, active mode (am) i am,1mhz bcsctl1 = calbc1_1mhz, a current (1 mhz) 3.3 v 340 dcoctl = caldco_1mhz, cpuoff = 0, scg0 = 0, scg1 = 0, oscoff = 0 f mclk = f smclk = f aclk = 32768 hz/8 = -40 c to 5 9 4096 hz, 85 c 2.2 v f dco = 0 hz, 105 c 18 active mode (am) program executes in flash, i am,4khz a -40 c to current (4 khz) selmx = 11, sels = 1, 6 10 85 c divmx = divsx = divax = 11, 3 v cpuoff = 0, scg0 = 1, scg1 = 0, 105 c 20 oscoff = 0 -40 c to 60 85 85 c f mclk = f smclk = f dco(0, 0) 100 khz, 2.2 v f aclk = 0 hz, 105 c 95 active mode (am) i am,100khz program executes in flash, a current (100 khz) -40 c to rselx = 0, dcox = 0, cpuoff = 0, 72 95 85 c 3 v scg0 = 0, scg1 = 0, oscoff = 1 105 c 105 (1) all inputs are tied to 0 v or v cc . outputs do not source or sink any current. (2) the currents are characterized with a micro crystal cc4v-t1a smd crystal with a load capacitance of 9 pf. the internal and external load capacitance is chosen to closely match the required 9 pf. copyright ? 2006 ? 2012, texas instruments incorporated 27
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com typical characteristics - active-mode supply current (into dv cc + av cc ) active-mode current vs active-mode current supply voltage vs t a = 25 c dco frequency figure 2. figure 3. 28 copyright ? 2006 ? 2012, texas instruments incorporated 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 1.5 2.0 2.5 3.0 3.5 4.0 v cc ? supply voltage ? v active mode current ? ma f dco = 1 mhz f dco = 8 mhz f dco = 12 mhz f dco = 16 mhz 0.0 1.0 2.0 3.0 4.0 5.0 0.0 4.0 8.0 12.0 16.0 f dco ? dco frequency ? mhz active mode current ? ma t a = 25 c t a = 85 c v cc = 2.2 v v cc = 3 v t a = 25 c t a = 85 c
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 low-power-mode supply currents (into v cc ) excluding external current (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions t a v cc min typ max unit f mclk = 0 mhz, 2.2 v 75 90 f smclk = f dco = 1 mhz, f aclk = 32768 hz, low-power mode 0 i lpm0,1mhz bcsctl1 = calbc1_1mhz, a (lpm0) current (3) 3 v 90 120 dcoctl = caldco_1mhz, cpuoff = 1, scg0 = 0, scg1 = 0, oscoff = 0 f mclk = 0 mhz, 2.2 v 37 48 f smclk = f dco(0, 0) 100 khz, low-power mode 0 f aclk = 0 hz, i lpm0,100khz a (lpm0) current (3) rselx = 0, dcox = 0, 3 v 41 65 cpuoff = 1, scg0 = 0, scg1 = 0, oscoff = 1 -40 c to f mclk = f smclk = 0 mhz, 22 29 85 c f dco = 1 mhz, 2.2 v f aclk = 32768 hz, 105 c 31 low-power mode 2 i lpm2 bcsctl1 = calbc1_1mhz, a (lpm2) current (4) -40 c to dcoctl = caldco_1mhz, 25 32 85 c 3 v cpuoff = 1, scg0 = 0, scg1 = 1, oscoff = 0 105 c 34 -40 c 0.7 1.4 25 c 0.7 1.4 2.2 v 85 c 2.4 3.3 f dco = f mclk = f smclk = 0 mhz, 105 c 5 10 low-power mode 3 f aclk = 32768 hz, i lpm3,lfxt1 a (lpm3) current (4) cpuoff = 1, scg0 = 1, -40 c 0.9 1.5 scg1 = 1, oscoff = 0 25 c 0.9 1.5 3 v 85 c 2.6 3.8 105 c 6 12 -40 c 0.4 1 25 c 0.5 1 2.2 v 85 c 1.8 2.9 f dco = f mclk = f smclk = 0 mhz, f aclk from internal lf oscillator 105 c 4.5 9 low-power mode 3 i lpm3,vlo (vlo), a current, (lpm3) (4) -40 c 0.5 1.2 cpuoff = 1, scg0 = 1, scg1 = 1, oscoff = 0 25 c 0.6 1.2 3 v 85 c 2.1 3.3 105 c 5.5 11 -40 c 0.1 0.5 f dco = f mclk = f smclk = 0 mhz, 25 c 0.1 0.5 low-power mode 4 f aclk = 0 hz, 2.2 v/ i lpm4 a (lpm4) current (5) cpuoff = 1, scg0 = 1, 3 v 85 c 1.5 3 scg1 = 1, oscoff = 1 105 c 4.5 9 (1) all inputs are tied to 0 v or v cc . outputs do not source or sink any current. (2) the currents are characterized with a micro crystal cc4v-t1a smd crystal with a load capacitance of 9 pf. the internal and external load capacitance is chosen to closely match the required 9 pf. (3) current for brownout and wdt clocked by smclk included. (4) current for brownout and wdt clocked by aclk included. (5) current for brownout included. copyright ? 2006 ? 2012, texas instruments incorporated 29
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com schmitt-trigger inputs (ports p1, p2, p3, p4, and rst/nmi) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit 0.45 v cc 0.75 v cc v it+ positive-going input threshold voltage 2.2 v 1 1.65 v 3 v 1.35 2.25 0.25 v cc 0.55 v cc v it- negative-going input threshold voltage 2.2 v 0.55 1.20 v 3 v 0.75 1.65 2.2 v 0.1 1 v hys input voltage hysteresis (v it+ - v it- ) v 3 v 0.3 1 for pullup: v in = v ss , r pull pullup/pulldown resistor 3 v 20 35 50 k ? for pulldown: v in = v cc c i input capacitance v in = v ss or v cc 5 pf inputs (ports p1, p2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit port p1, p2: p1.x to p2.x, external trigger t (int) external interrupt timing 2.2 v, 3 v 20 ns pulse width to set interrupt flag (1) (1) an external signal sets the interrupt flag every time the minimum interrupt pulse width t (int) is met. it may be set even with trigger signals shorter than t (int) . leakage current (ports p1, p2, p3, and p4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit i lkg(px.y) high-impedance leakage current (1) (2) 2.2 v, 3 v 50 na (1) the leakage current is measured with v ss or v cc applied to the corresponding pin(s), unless otherwise noted. (2) the leakage of the digital port pins is measured individually. the port pin is selected for input and the pullup/pulldown resistor is disabled. 30 copyright ? 2006 ? 2012, texas instruments incorporated
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 outputs (ports p1, p2, p3, and p4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min max unit i oh(max) = -1.5 ma (1) v cc - 0.25 v cc 2.2 v i oh(max) = -6 ma (2) v cc - 0.6 v cc v oh high-level output voltage v i oh(max) = -1.5 ma (1) v cc - 0.25 v cc 3 v i oh(max) = -6 ma (2) v cc - 0.6 v cc i ol(max) = 1.5 ma (1) v ss v ss + 0.25 2.2 v i ol(max) = 6 ma (2) v ss v ss + 0.6 v ol low-level output voltage v i ol(max) = 1.5 ma (1) v ss v ss + 0.25 3 v i ol(max) = 6 ma (2) v ss v ss + 0.6 (1) the maximum total current, i oh(max) and i ol(max) , for all outputs combined, should not exceed 12 ma to hold the maximum voltage drop specified. (2) the maximum total current, i oh(max) and i ol(max) , for all outputs combined, should not exceed 48 ma to hold the maximum voltage drop specified. output frequency (ports p1, p2, p3, and p4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit 2.2 v 10 p1.4/smclk, c l = 20 pf, f px.y port output frequency (with load) mhz r l = 1 k ? against v cc /2 (1) (2) 3 v 12 2.2 v 12 f port_clk clock output frequency p2.0/aclk, p1.4/smclk, c l = 20 pf (2) mhz 3 v 16 (1) alternatively, a resistive divider with two 2-k ? resistors between v cc and v ss is used as load. the output is connected to the center tap of the divider. (2) the output voltage reaches at least 10% and 90% v cc at the specified toggle frequency. copyright ? 2006 ? 2012, texas instruments incorporated 31
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com typical characteristics - outputs one output loaded at a time. typical low-level output current typical low-level output current vs vs low-level output voltage low-level output voltage figure 4. figure 5. typical high-level output current typical high-level output current vs vs high-level output voltage high-level output voltage figure 6. figure 7. 32 copyright ? 2006 ? 2012, texas instruments incorporated v oh ? high-level output v oltage ? v ?25.0 ?20.0 ?15.0 ?10.0 ?5.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 v cc = 2.2 v p4.5 t a = 25c t a = 85c oh i ? typical high-level output current ? ma v oh ? high-level output v oltage ? v ?50.0 ?40.0 ?30.0 ?20.0 ?10.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v cc = 3 v p4.5 t a = 25c t a = 85c oh i ? typical high-level output current ? ma v ol ? low-level output v oltage ? v 0.0 5.0 10.0 15.0 20.0 25.0 0.0 0.5 1.0 1.5 2.0 2.5 v cc = 2.2 v p4.5 t a = 25c t a = 85c ol i ? typical low-level output current ? ma v ol ? low-level output v oltage ? v 0.0 10.0 20.0 30.0 40.0 50.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v cc = 3 v p4.5 t a = 25c t a = 85c ol i ? typical low-level output current ? ma
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 por/brownout reset (bor) (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit 0.7 v cc(start) see figure 8 dv cc /dt 3 v/s v v (b_it-) v (b_it-) see figure 8 through figure 10 dv cc /dt 3 v/s 1.71 v v hys(b_it-) see figure 8 dv cc /dt 3 v/s 70 130 210 mv t d(bor) see figure 8 2000 s pulse length needed at rst/nmi pin t (reset) 3 v 2 s to accepted reset internally (1) the current consumption of the brownout module is already included in the i cc current consumption data. the voltage level v (b_it-) + v hys(b_it-) is 1.8 v. (2) during power up, the cpu begins code execution following a period of t d(bor) after v cc = v (b_it-) + v hys(b_it-) . the default dco settings must not be changed until v cc v cc(min) , where v cc(min) is the minimum supply voltage for the desired operating frequency. figure 8. por/brownout reset (bor) vs supply voltage copyright ? 2006 ? 2012, texas instruments incorporated 33 0 1 t d(bor) v cc v (b_it?) v hys(b_it?) v cc(start)
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com typical characteristics - por/brownout reset (bor) figure 9. v cc(drop) level with a square voltage drop to generate a por/brownout signal figure 10. v cc(drop) level with a triangle voltage drop to generate a por/brownout signal 34 copyright ? 2006 ? 2012, texas instruments incorporated v cc 0 0.5 1 1.5 2 v cc(drop) t pw t pw ? pulse width ? s v cc(drop) ? v 3 v 0.001 1 1000 t f t r t pw ? pulse width ? s t f = t r typical conditions v cc = 3 v v cc(drop) v cc 3 v t pw 0 0.5 1 1.5 2 0.001 1 1000 typical conditions 1 ns 1 ns t pw ? pulse width ? s v cc(drop) ? v t pw ? pulse width ? s v cc = 3 v
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 main dco characteristics ? all ranges selected by rselx overlap with rselx + 1: rselx = 0 overlaps rselx = 1, ... rselx = 14 overlaps rselx = 15. ? dco control bits dcox have a step size as defined by parameter s dco . ? modulation control bits modx select how often f dco(rsel,dco+1) is used within the period of 32 dcoclk cycles. the frequency f dco(rsel,dco) is used for the remaining cycles. the frequency is an average equal to: dco frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit rselx < 14 1.8 3.6 v cc supply voltage range rselx = 14 2.2 3.6 v rselx = 15 3.0 3.6 f dco(0,0) dco frequency (0, 0) rselx = 0, dcox = 0, modx = 0 2.2 v, 3 v 0.06 0.14 mhz f dco(0,3) dco frequency (0, 3) rselx = 0, dcox = 3, modx = 0 2.2 v, 3 v 0.07 0.17 mhz f dco(1,3) dco frequency (1, 3) rselx = 1, dcox = 3, modx = 0 2.2 v, 3 v 0.10 0.20 mhz f dco(2,3) dco frequency (2, 3) rselx = 2, dcox = 3, modx = 0 2.2 v, 3 v 0.14 0.28 mhz f dco(3,3) dco frequency (3, 3) rselx = 3, dcox = 3, modx = 0 2.2 v, 3 v 0.20 0.40 mhz f dco(4,3) dco frequency (4, 3) rselx = 4, dcox = 3, modx = 0 2.2 v, 3 v 0.28 0.54 mhz f dco(5,3) dco frequency (5, 3) rselx = 5, dcox = 3, modx = 0 2.2 v, 3 v 0.39 0.77 mhz f dco(6,3) dco frequency (6, 3) rselx = 6, dcox = 3, modx = 0 2.2 v, 3 v 0.54 1.06 mhz f dco(7,3) dco frequency (7, 3) rselx = 7, dcox = 3, modx = 0 2.2 v, 3 v 0.80 1.50 mhz f dco(8,3) dco frequency (8, 3) rselx = 8, dcox = 3, modx = 0 2.2 v, 3 v 1.10 2.10 mhz f dco(9,3) dco frequency (9, 3) rselx = 9, dcox = 3, modx = 0 2.2 v, 3 v 1.60 3.00 mhz f dco(10,3) dco frequency (10, 3) rselx = 10, dcox = 3, modx = 0 2.2 v, 3 v 2.50 4.30 mhz f dco(11,3) dco frequency (11, 3) rselx = 11, dcox = 3, modx = 0 2.2 v, 3 v 3.00 5.50 mhz f dco(12,3) dco frequency (12, 3) rselx = 12, dcox = 3, modx = 0 2.2 v, 3 v 4.30 7.30 mhz f dco(13,3) dco frequency (13, 3) rselx = 13, dcox = 3, modx = 0 2.2 v, 3 v 6.00 9.60 mhz f dco(14,3) dco frequency (14, 3) rselx = 14, dcox = 3, modx = 0 2.2 v, 3 v 8.60 13.9 mhz f dco(15,3) dco frequency (15, 3) rselx = 15, dcox = 3, modx = 0 3 v 12.0 18.5 mhz f dco(15,7) dco frequency (15, 7) rselx = 15, dcox = 7, modx = 0 3 v 16.0 26.0 mhz frequency step between s rsel s rsel = f dco(rsel+1,dco) /f dco(rsel,dco) 2.2 v, 3 v 1.55 ratio range rsel and rsel+1 frequency step between tap s dco s dco = f dco(rsel,dco+1) /f dco(rsel,dco) 2.2 v, 3 v 1.05 1.08 1.12 ratio dco and dco+1 duty cycle measured at p1.4/smclk 2.2 v, 3 v 40 50 60 % copyright ? 2006 ? 2012, texas instruments incorporated 35 dco(rsel,dco) dco(rsel,dco+1) average dco(rsel,dco) dco(rsel,dco+1) 32 f f f = mod f + (32 C mod) f
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com calibrated dco frequencies - tolerance at calibration over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions t a v cc min typ max unit frequency tolerance at calibration 25 c 3 v -1 0.2 +1 % bcsctl1 = calbc1_1mhz, f cal(1mhz) 1-mhz calibration value dcoctl = caldco_1mhz, 25 c 3 v 0.990 1 1.010 mhz gating time: 5 ms bcsctl1 = calbc1_8mhz, f cal(8mhz) 8-mhz calibration value dcoctl = caldco_8mhz, 25 c 3 v 7.920 8 8.080 mhz gating time: 5 ms bcsctl1 = calbc1_12mhz, f cal(12mhz) 12-mhz calibration value dcoctl = caldco_12mhz, 25 c 3 v 11.88 12 12.12 mhz gating time: 5 ms bcsctl1 = calbc1_16mhz, f cal(16mhz) 16-mhz calibration value dcoctl = caldco_16mhz, 25 c 3 v 15.84 16 16.16 mhz gating time: 2 ms calibrated dco frequencies - tolerance over temperature 0 c to 85 c over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions t a v cc min typ max unit 1-mhz tolerance over 0 c to 85 c 3 v -2.5 0.5 +2.5 % temperature 8-mhz tolerance over 0 c to 85 c 3 v -2.5 1.0 +2.5 % temperature 12-mhz tolerance over 0 c to 85 c 3 v -2.5 1.0 +2.5 % temperature 16-mhz tolerance over 0 c to 85 c 3 v -3 2.0 +3 % temperature 2.2 v 0.97 1 1.03 bcsctl1 = calbc1_1mhz, f cal(1mhz) 1-mhz calibration value dcoctl = caldco_1mhz, 0 c to 85 c 3 v 0.975 1 1.025 mhz gating time: 5 ms 3.6 v 0.97 1 1.03 2.2 v 7.76 8 8.4 bcsctl1 = calbc1_8mhz, f cal(8mhz) 8-mhz calibration value dcoctl = caldco_8mhz, 0 c to 85 c 3 v 7.8 8 8.2 mhz gating time: 5 ms 3.6 v 7.6 8 8.24 2.2 v 11.7 12 12.3 bcsctl1 = calbc1_12mhz, f cal(12mhz) 12-mhz calibration value dcoctl = caldco_12mhz, 0 c to 85 c 3 v 11.7 12 12.3 mhz gating time: 5 ms 3.6 v 11.7 12 12.3 bcsctl1 = calbc1_16mhz, 3 v 15.52 16 16.48 f cal(16mhz) 16-mhz calibration value dcoctl = caldco_16mhz, 0 c to 85 c mhz 3.6 v 15 16 16.48 gating time: 2 ms 36 copyright ? 2006 ? 2012, texas instruments incorporated
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 calibrated dco frequencies - tolerance over supply voltage v cc over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions t a v cc min typ max unit 1-mhz tolerance over v cc 25 c 1.8 v to 3.6 v -3 2 +3 % 8-mhz tolerance over v cc 25 c 1.8 v to 3.6 v -3 2 +3 % 12-mhz tolerance over v cc 25 c 2.2 v to 3.6 v -3 2 +3 % 16-mhz tolerance over v cc 25 c 3 v to 3.6 v -6 2 +3 % bcsctl1 = calbc1_1mhz, f cal(1mhz) 1-mhz calibration value dcoctl = caldco_1mhz, 25 c 1.8 v to 3.6 v 0.97 1 1.03 mhz gating time: 5 ms bcsctl1 = calbc1_8mhz, f cal(8mhz) 8-mhz calibration value dcoctl = caldco_8mhz, 25 c 1.8 v to 3.6 v 7.76 8 8.24 mhz gating time: 5 ms bcsctl1 = calbc1_12mhz, f cal(12mhz) 12-mhz calibration value dcoctl = caldco_12mhz, 25 c 2.2 v to 3.6 v 11.64 12 12.36 mhz gating time: 5 ms bcsctl1 = calbc1_16mhz, f cal(16mhz) 16-mhz calibration value dcoctl = caldco_16mhz, 25 c 3 v to 3.6 v 15 16 16.48 mhz gating time: 2 ms calibrated dco frequencies - overall tolerance over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions t a v cc min typ max unit 1-mhz tolerance i: -40 c to 85 c 1.8 v to 3.6 v -5 2 +5 % overall t: -40 c to 105 c 8-mhz tolerance i: -40 c to 85 c 1.8 v to 3.6 v -5 2 +5 % overall t: -40 c to 105 c 12-mhz i: -40 c to 85 c 2.2 v to 3.6 v -5 2 +5 % tolerance overall t: -40 c to 105 c 16-mhz i: -40 c to 85 c 3 v to 3.6 v -6 3 +6 % tolerance overall t: -40 c to 105 c bcsctl1 = calbc1_1mhz, 1-mhz i: -40 c to 85 c f cal(1mhz) dcoctl = caldco_1mhz, 1.8 v to 3.6 v 0.95 1 1.05 mhz calibration value t: -40 c to 105 c gating time: 5 ms bcsctl1 = calbc1_8mhz, 8-mhz i: -40 c to 85 c f cal(8mhz) dcoctl = caldco_8mhz, 1.8 v to 3.6 v 7.6 8 8.4 mhz calibration value t: -40 c to 105 c gating time: 5 ms bcsctl1 = calbc1_12mhz, 12-mhz i: -40 c to 85 c f cal(12mhz) dcoctl = caldco_12mhz, 2.2 v to 3.6 v 11.4 12 12.6 mhz calibration value t: -40 c to 105 c gating time: 5 ms bcsctl1 = calbc1_16mhz, 16-mhz i: -40 c to 85 c f cal(16mhz) dcoctl = caldco_16mhz, 3 v to 3.6 v 15 16 17 mhz calibration value t: -40 c to 105 c gating time: 2 ms copyright ? 2006 ? 2012, texas instruments incorporated 37
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com typical characteristics - calibrated 1-mhz dco frequency calibrated 1-mhz frequency calibrated 1-mhz frequency vs vs temperature supply voltage figure 11. figure 12. 38 copyright ? 2006 ? 2012, texas instruments incorporated v cc ? supply voltage ? v 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.5 2.0 2.5 3.0 3.5 4.0 frequency ? mhz t a = ?40 c t a = 25 c t a = 85 c t a = 105 c t a ? temperature ? c 0.97 0.98 0.99 1.00 1.01 1.02 1.03 ?50.0 ?25.0 0.0 25.0 50.0 75.0 100.0 frequency ? mhz v cc = 1.8 v v cc = 2.2 v v cc = 3.0 v v cc = 3.6 v
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 wake-up from lower-power modes (lpm3/4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit bcsctl1 = calbc1_1mhz, 2 dcoctl = caldco_1mhz bcsctl1 = calbc1_8mhz, 2.2 v, 3 v 1.5 dcoctl = caldco_8mhz dco clock wake-up time t dco,lpm3/4 s from lpm3/4 (1) bcsctl1 = calbc1_12mhz, 1 dcoctl = caldco_12mhz bcsctl1 = calbc1_16mhz, 3 v 1 dcoctl = caldco_16mhz cpu wake-up time from 1 / f mclk + t cpu,lpm3/4 lpm3/4 (2) t clock,lpm3/4 (1) the dco clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock edge observable externally on a clock pin (mclk or smclk). (2) parameter applicable only if dcoclk is used for mclk. typical characteristics - dco clock wake-up time from lpm3/4 clock wake-up time from lpm3 vs dco frequency figure 13. copyright ? 2006 ? 2012, texas instruments incorporated 39 dco frequency ? mhz 0.10 1.00 10.00 0.10 1.00 10.00 rselx = 0...11 rselx = 12...15 dco wake-up time ? s
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com dco with external resistor r osc (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit dcor = 1, 2.2 v 1.8 f dco,rosc dco output frequency with r osc rselx = 4, dcox = 3, modx = 0, mhz 3 v 1.95 t a = 25 c dcor = 1, d t temperature drift 2.2 v, 3 v 0.1 %/ c rselx = 4, dcox = 3, modx = 0 dcor = 1, d v drift with v cc 2.2 v, 3 v 10 %/v rselx = 4, dcox = 3, modx = 0 (1) r osc = 100 k . metal film resistor, type 0257, 0.6 w with 1% tolerance and t k = 50 ppm/ c. typical characteristics - dco with external resistor r osc dco frequency dco frequency vs vs r osc r osc v cc = 2.2 v, t a = 25 c v cc = 3 v, t a = 25 c figure 14. figure 15. dco frequency dco frequency vs vs temperature supply voltage v cc = 3 v t a = 25 c figure 16. figure 17. 40 copyright ? 2006 ? 2012, texas instruments incorporated 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 ?50.0 ?25.0 0.0 25.0 50.0 75.0 100.0 t a ? temperature ? c dco frequency ? mhz r osc = 100k r osc = 270k r osc = 1m 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.0 2.5 3.0 3.5 4.0 v cc ? supply voltage ? v dco frequency ? mhz r osc = 100k r osc = 270k r osc = 1m 0.01 0.10 1.00 10.00 10.00 100.00 1000.00 10000.00 r osc ? external resistor ? k w dco frequency ? mhz rselx = 4 0.01 0.10 1.00 10.00 10.00 100.00 1000.00 10000.00 r osc ? external resistor ? k w dco frequency ? mhz rselx = 4
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 crystal oscillator lfxt1, low-frequency mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit lfxt1 oscillator crystal f lfxt1,lf xts = 0, lfxt1sx = 0 or 1 1.8 v to 3.6 v 32768 hz frequency, lf mode 0, 1 lfxt1 oscillator logic level f lfxt1,lf,logic square wave input frequency, xts = 0, lfxt1sx = 3 1.8 v to 3.6 v 10000 32768 50000 hz lf mode xts = 0, lfxt1sx = 0, 500 f lfxt1,lf = 32768 hz, c l,eff = 6 pf oscillation allowance for oa lf k ? lf crystals xts = 0, lfxt1sx = 0, 200 f lfxt1,lf = 32768 hz, c l,eff = 12 pf xts = 0, xcapx = 0 1 xts = 0, xcapx = 1 5.5 integrated effective load c l,eff pf capacitance, lf mode (2) xts = 0, xcapx = 2 8.5 xts = 0, xcapx = 3 11 xts = 0, measured at p2.0/aclk, duty cycle, lf mode 2.2 v, 3 v 30 50 70 % f lfxt1,lf = 32768 hz oscillator fault frequency, f fault,lf xts = 0, lfxt1sx = 3 (4) 2.2 v, 3 v 10 10000 hz lf mode (3) (1) to improve emi on the xt1 oscillator, the following guidelines should be observed. ( a) keep the trace between the device and the crystal as short as possible. ( b) design a good ground plane around the oscillator pins. ( c) prevent crosstalk from other clock or data lines into oscillator pins xin and xout. ( d) avoid running pcb traces underneath or adjacent to the xin and xout pins. ( e) use assembly materials and praxis to avoid any parasitic load on the oscillator xin and xout pins. ( f) if conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins. ( g) do not route the xout line to the jtag header to support the serial programming adapter as shown in other documentation. this signal is no longer required for the serial programming adapter. (2) includes parasitic bond and package capacitance (approximately 2 pf per pin). because the pcb adds additional capacitance, it is recommended to verify the correct load by measuring the aclk frequency. for a correct setup, the effective load capacitance should always match the specification of the crystal that is used. (3) frequencies below the min specification set the fault flag. frequencies above the max specification do not set the fault flag. frequencies in between might set the flag. (4) measured with logic-level input frequency but also applies to operation with crystals. internal very-low-power low-frequency oscillator (vlo) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter t a v cc min typ max unit -40 c to 85 c 4 12 20 f vlo vlo frequency 2.2 v, 3 v khz 105 c 22 i: -40 c to 85 c df vlo /dt vlo frequency temperature drift (1) 2.2 v, 3 v 0.5 %/ c t: -40 c to 105 c df vlo /dv cc vlo frequency supply voltage drift (2) 25 c 1.8 v to 3.6 v 4 %/v (1) calculated using the box method: i version: [max(-40...85 c) - min(-40...85 c)]/min(-40...85 c)/[85 c - (-40 c)] t version: [max(-40...105 c) - min(-40...105 c)]/min(-40...105 c)/[105 c - (-40 c)] (2) calculated using the box method: [max(1.8...3.6 v) - min(1.8...3.6 v)]/min(1.8...3.6 v)/(3.6 v - 1.8 v) copyright ? 2006 ? 2012, texas instruments incorporated 41
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com crystal oscillator lfxt1, high-frequency mode (1) parameter test conditions v cc min typ max unit lfxt1 oscillator crystal f lfxt1,hf0 xts = 1, lfxt1sx = 0 1.8 v to 3.6 v 0.4 1 mhz frequency, hf mode 0 lfxt1 oscillator crystal f lfxt1,hf1 xts = 1, lfxt1sx = 1 1.8 v to 3.6 v 1 4 mhz frequency, hf mode 1 1.8 v to 3.6 v 2 10 lfxt1 oscillator crystal f lfxt1,hf2 xts = 1, lfxt1sx = 2 2.2 v to 3.6 v 2 12 mhz frequency, hf mode 2 3 v to 3.6 v 2 16 1.8 v to 3.6 v 0.4 10 lfxt1 oscillator logic-level f lfxt1,hf,logic square-wave input frequency, hf xts = 1, lfxt1sx = 3 2.2 v to 3.6 v 0.4 12 mhz mode 3 v to 3.6 v 0.4 16 xts = 1, lfxt1sx = 0, f lfxt1,hf = 1 mhz, 2700 c l,eff = 15 pf oscillation allowance for hf xts = 1, lfxt1sx = 1, oa hf crystals (see figure 18 and f lfxt1,hf = 4 mhz, 800 ? figure 19 ) c l,eff = 15 pf xts = 1, lfxt1sx = 2, f lfxt1,hf = 16 mhz, 300 c l,eff = 15 pf integrated effective load c l,eff xts = 1 (3) 1 pf capacitance, hf mode (2) xts = 1, measured at p2.0/aclk, 40 50 60 f lfxt1,hf = 10 mhz duty cycle, hf mode 2.2 v, 3 v % xts = 1, measured at p2.0/aclk, 40 50 60 f lfxt1,hf = 16 mhz f fault,hf oscillator fault frequency (4) xts = 1, lfxt1sx = 3 (5) 2.2 v, 3 v 30 300 khz (1) to improve emi on the xt1 oscillator the following guidelines should be observed: ( a) keep the trace between the device and the crystal as short as possible. ( b) design a good ground plane around the oscillator pins. ( c) prevent crosstalk from other clock or data lines into oscillator pins xin and xout. ( d) avoid running pcb traces underneath or adjacent to the xin and xout pins. ( e) use assembly materials and praxis to avoid any parasitic load on the oscillator xin and xout pins. ( f) if conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins. ( g) do not route the xout line to the jtag header to support the serial programming adapter as shown in other documentation. this signal is no longer required for the serial programming adapter. (2) includes parasitic bond and package capacitance (approximately 2 pf per pin). because the pcb adds additional capacitance, it is recommended to verify the correct load by measuring the aclk frequency. for a correct setup, the effective load capacitance should always match the specification of the used crystal. (3) requires external capacitors at both terminals. values are specified by crystal manufacturers. (4) frequencies below the min specification set the fault flag, frequencies above the max specification do not set the fault flag, and frequencies in between might set the flag. (5) measured with logic-level input frequency, but also applies to operation with crystals. 42 copyright ? 2006 ? 2012, texas instruments incorporated
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 typical characteristics - lfxt1 oscillator in hf mode (xts = 1) oscillation allowance oscillator supply current vs vs crystal frequency crystal frequency c l,eff = 15 pf, t a = 25 c c l,eff = 15 pf, t a = 25 c figure 18. figure 19. timer_a over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit internal: smclk, aclk 2.2 v 10 f ta timer_a clock frequency external: taclk, inclk mhz 3 v 16 duty cycle = 50% 10% t ta,cap timer_a capture timing ta0, ta1, ta2 2.2 v, 3 v 20 ns timer_b over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit internal: smclk, aclk 2.2 v 10 f tb timer_b clock frequency external: taclk, inclk mhz 3 v 16 duty cycle = 50% 10% t tb,cap timer_b capture timing tb0, tb1, tb2 2.2 v, 3 v 20 ns copyright ? 2006 ? 2012, texas instruments incorporated 43 0.0 100.0 200.0 300.0 400.0 500.0 600.0 700.0 800.0 0.0 4.0 8.0 12.0 16.0 20.0 crystal frequency ? mhz xt oscillator supply current ? ua lfxt1sx = 1 lfxt1sx = 3 lfxt1sx = 2 crystal frequency ? mhz 10.00 100.00 1000.00 10000.00 100000.00 0.10 1.00 10.00 100.00 oscillation allowance ? ohms lfxt1sx = 1 lfxt1sx = 3 lfxt1sx = 2
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com usci (uart mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter conditions v cc min typ max unit internal: smclk, aclk f usci usci input clock frequency external: uclk f system mhz duty cycle = 50% 10% bitclk clock frequency f bitclk 2.2 v, 3 v 1 mhz (equals baud rate in mbaud) 2.2 v 50 150 600 t uart receive deglitch time (1) ns 3 v 50 100 600 (1) pulses on the uart receive input (ucxrx) shorter than the uart receive deglitch time are suppressed. to ensure that pulses are correctly recognized their width should exceed the maximum specification of the deglitch time. usci (spi master mode) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see figure 20 and figure 21 ) parameter test conditions v cc min typ max unit smclk, aclk f usci usci input clock frequency f system mhz duty cycle = 50% 10% 2.2 v 110 t su,mi somi input data setup time ns 3 v 75 2.2 v 0 t hd,mi somi input data hold time ns 3 v 0 2.2 v 30 uclk edge to simo valid, t valid,mo simo output data valid time ns c l = 20 pf 3 v 20 (1) f ucxclk = 1/2t lo/hi with t lo/hi max(t valid,mo(usci) + t su,si(slave) , t su,mi(usci) + t valid,so(slave) ). for the slave ' s parameters t su,si(slave) and t valid,so(slave) , see the spi parameters of the attached slave. usci (spi slave mode) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see figure 22 and figure 23 ) parameter test conditions v cc min typ max unit t ste,lead ste lead time, ste low to clock 2.2 v, 3 v 50 ns t ste,lag ste lag time, last clock to ste high 2.2 v, 3 v 10 ns t ste,acc ste access time, ste low to somi data out 2.2 v, 3 v 50 ns ste disable time, ste high to somi high t ste,dis 2.2 v, 3 v 50 ns impedance 2.2 v 20 t su,si simo input data setup time ns 3 v 15 2.2 v 10 t hd,si simo input data hold time ns 3 v 10 2.2 v 75 110 uclk edge to somi valid, t valid,so somi output data valid time ns c l = 20 pf 3 v 50 75 (1) f ucxclk = 1/2t lo/hi with t lo/hi max(t valid,mo(master) + t su,si(usci) , t su,mi(master) + t valid,so(usci) ). for the master ' s parameters t su,mi(master) and t valid,mo(master) refer to the spi parameters of the attached slave. 44 copyright ? 2006 ? 2012, texas instruments incorporated
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 figure 20. spi master mode, ckph = 0 figure 21. spi master mode, ckph = 1 copyright ? 2006 ? 2012, texas instruments incorporated 45 uclk ckpl=0 ckpl=1 simo 1/f ucxclk t lo/hi t lo/hi somi t su,mi t hd,mi t valid,mo uclk ckpl=0 ckpl=1 simo 1/f ucxclk t lo/hi t lo/hi somi t su,mi t hd,mi t valid,mo
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com figure 22. spi slave mode, ckph = 0 figure 23. spi slave mode, ckph = 1 46 copyright ? 2006 ? 2012, texas instruments incorporated ste uclk ckpl=0 ckpl=1 somi t ste,acc t ste,dis 1/f ucxclk t lo/hi t lo/hi simo t su,si t hd,si t valid,so t ste,lead t ste,lag ste uclk ckpl=0 ckpl=1 t ste,lead t ste,lag t ste,acc t ste,dis t lo/hi t lo/hi t su,si t hd,si t valid,so somi simo 1/f ucxclk
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 usci (i2c mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see figure 24 ) parameter test conditions v cc min typ max unit internal: smclk, aclk f usci usci input clock frequency external: uclk f system mhz duty cycle = 50% 10% f scl scl clock frequency 2.2 v, 3 v 0 400 khz f scl 100 khz 4 t hd,sta hold time (repeated) start 2.2 v, 3 v s f scl > 100 khz 0.6 f scl 100 khz 4.7 t su,sta setup time for a repeated start 2.2 v, 3 v s f scl > 100 khz 0.6 t hd,dat data hold time 2.2 v, 3 v 0 ns t su,dat data setup time 2.2 v, 3 v 250 ns t su,sto setup time for stop 2.2 v, 3 v 4 s 2.2 v 50 150 600 t sp pulse width of spikes suppressed by input filter ns 3 v 50 100 600 figure 24. i2c mode timing copyright ? 2006 ? 2012, texas instruments incorporated 47 sda scl 1/f scl t hd,dat t su,dat t hd,sta t su,sta t hd,sta t su,sto t sp
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com 10-bit adc, power supply and input range conditions (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) parameter test conditions t a v cc min typ max unit analog supply voltage v cc v ss = 0 v 2.2 3.6 v range all ax terminals, analog input voltage v ax analog inputs selected in 0 v cc v range (2) adc10ae register f adc10clk = 5 mhz, 2.2 v 0.52 1.05 adc10on = 1, refon = 0, i: -40 c to 85 c i adc10 adc10 supply current (3) adc10sht0 = 1, ma t: -40 c to 105 c 3 v 0.6 1.2 adc10sht1 = 0, adc10div = 0 f adc10clk = 5 mhz, adc10on = 0, ref2_5v = 0, 2.2 v, 3 v 0.25 0.4 reference supply refon = 1, refout = 0 i: -40 c to 85 c i ref+ current, reference buffer ma t: -40 c to 105 c f adc10clk = 5 mhz, disabled (4) adc10on = 0, ref2_5v = 1, 3 v 0.25 0.4 refon = 1, refout = 0 f adc10clk = 5 mhz -40 c to 85 c 2.2 v, 3 v 1.1 1.4 reference buffer supply adc10on = 0, refon = 1, i refb,0 current with ma ref2_5v = 0, refout = 1, 105 c 2.2 v, 3 v 1.8 adc10sr = 0 (4) adc10sr = 0 f adc10clk = 5 mhz, -40 c to 85 c 2.2 v, 3 v 0.5 0.7 reference buffer supply adc10on = 0, refon = 1, i refb,1 current with ma ref2_5v = 0, refout = 1, 105 c 2.2 v, 3 v 0.8 adc10sr = 1 (4) adc10sr = 1 only one terminal ax selected at i: -40 c to 85 c c i input capacitance 27 pf a time t: -40 c to 105 c input mux on i: -40 c to 85 c r i 0 v v ax v cc 2.2 v, 3 v 2000 resistance t: -40 c to 105 c (1) the leakage current is defined in the leakage current table with px.x/ax parameter. (2) the analog input voltage range must be within the selected reference voltage range v r+ to v r- for valid conversion results. (3) the internal reference supply current is not included in current consumption parameter i adc10 . (4) the internal reference current is supplied via terminal v cc . consumption is independent of the adc10on control bit, unless a conversion is active. the refon bit enables the built-in reference to settle before starting an a/d conversion. 48 copyright ? 2006 ? 2012, texas instruments incorporated
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 10-bit adc, built-in voltage reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit i vref+ 1 ma, ref2_5v = 0 2.2 positive built-in v cc,ref+ reference analog i vref+ 0.5 ma, ref2_5v = 1 2.8 v supply voltage range i vref+ 1 ma, ref2_5v = 1 2.9 i vref+ i vref+ max, ref2_5v = 0 2.2 v, 3 v 1.41 1.5 1.59 positive built-in v ref+ v reference voltage i vref+ i vref+ max, ref2_5v = 1 3 v 2.35 2.5 2.65 2.2 v 0.5 maximum v ref+ i ld,vref+ ma load current 3 v 1 i vref+ = 500 a 100 a, analog input voltage v ax 0.75 v, 2.2 v, 3 v 2 ref2_5v = 0 v ref+ load lsb regulation i vref+ = 500 a 100 a, analog input voltage v ax 1.25 v, 3 v 2 ref2_5v = 1 i vref+ = 100 a to 900 a, adc10sr = 0 400 v ref+ load v ax 0.5 x v ref+ , regulation response 3 v ns error of conversion result adc10sr = 1 2000 time 1 lsb maximum i vref+ 1 ma, c vref+ capacitance at pin 2.2 v, 3 v 100 pf refon = 1, refout = 1 v ref+ (1) temperature i vref+ = constant with t cref+ 2.2 v, 3 v 100 ppm/ c coefficient (2) 0 ma i vref+ 1 ma settling time of i vref+ = 0.5 ma, ref2_5v = 0, t refon internal reference 3.6 v 30 s refon = 0 to 1 voltage (3) i vref+ = 0.5 ma, adc10sr = 0 1 ref2_5v = 0, 2.2 v refon = 1, adc10sr = 1 2.5 refburst = 1 settling time of t refburst s reference buffer (3) i vref+ = 0.5 ma, adc10sr = 0 2 ref2_5v = 1, 3 v refon = 1, adc10sr = 1 4.5 refburst = 1 (1) the capacitance applied to the internal buffer operational amplifier, if switched to terminal p2.4/ta 2/a4/v ref+ / v eref+ (refout = 1), must be limited; the reference buffer may become unstable otherwise. (2) calculated using the box method: i temperature: (max(-40 to 85 c) ? min(-40 to 85 c)) / min(-40 to 85 c) / (85 c ? ( ? 40 c)) t temperature: (max(-40 to 105 c) ? min(-40 to 105 c)) / min(-40 to 105 c) / (105 c ? ( ? 40 c)) (3) the condition is that the error in a conversion started after t refon or t refbuf is less than 0.5 lsb. copyright ? 2006 ? 2012, texas instruments incorporated 49
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com 10-bit adc, external reference (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min max unit v eref+ > v eref- , 1.4 v cc sref1 = 1, sref0 = 0 positive external reference input v eref+ v voltage range (2) v eref- v eref+ v cc - 0.15 v, 1.4 3 sref1 = 1, sref0 = 1 (3) negative external reference input v eref- v eref+ > v eref- 0 1.2 v voltage range (4) differential external reference v eref input voltage range v eref+ > v eref- (5) 1.4 v cc v v eref = v eref+ - v eref- 0 v v eref+ v cc , 1 sref1 = 1, sref0 = 0 i veref+ static input current into v eref+ 2.2 v, 3 v a 0 v v eref+ v cc - 0.15 v 3 v, 0 sref1 = 1, sref0 = 1 (3) i veref- static input current into v eref- 0 v v eref- v cc 2.2 v, 3 v 1 a (1) the external reference is used during conversion to charge and discharge the capacitance array. the input capacitance, ci, is also the dynamic load for an external reference during conversion. the dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy. (2) the accuracy limits the minimum positive external reference voltage. lower reference voltage levels may be applied with reduced accuracy requirements. (3) under this condition, the external reference is internally buffered. the reference buffer is active and requires the reference buffer supply current i refb . the current consumption can be limited to the sample and conversion period with reburst = 1. (4) the accuracy limits the maximum negative external reference voltage. higher reference voltage levels may be applied with reduced accuracy requirements. (5) the accuracy limits the minimum external differential reference voltage. lower differential reference voltage levels may be applied with reduced accuracy requirements. 10-bit adc, timing parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit adc10sr = 0 0.45 6.3 adc10 input clock for specified performance of f adc10clk 2.2 v, 3 v mhz frequency adc10 linearity parameters adc10sr = 1 0.45 1.5 adc10 built-in oscillator adc10divx = 0, adc10sselx = 0, f adc10osc 2.2 v, 3 v 3.7 6.3 mhz frequency f adc10clk = f adc10osc adc10 built-in oscillator, adc10sselx = 0, 2.2 v, 3 v 2.06 3.51 f adc10clk = f adc10osc t convert conversion time s f adc10clk from aclk, mclk or smclk, 13 adc10divx adc10sselx 0 1 / f adc10clk turn on settling time of t adc10on 100 ns the adc (1) (1) the condition is that the error in a conversion started after t adc10on is less than 0.5 lsb. the reference and input signal are already settled. 50 copyright ? 2006 ? 2012, texas instruments incorporated
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 10-bit adc, linearity parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit e i integral linearity error 2.2 v, 3 v 1 lsb e d differential linearity error 2.2 v, 3 v 1 lsb e o offset error source impedance r s < 100 ? 2.2 v, 3 v 1 lsb srefx = 010, unbuffered external reference, 2.2 v 1.1 2 v eref+ = 1.5 v srefx = 010, unbuffered external reference, 3 v 1.1 2 v eref+ = 2.5 v e g gain error lsb srefx = 011, buffered external reference (1) , 2.2 v 1.1 4 v eref+ = 1.5 v srefx = 011, buffered external reference (1) , 3 v 1.1 3 v eref+ = 2.5 v srefx = 010, unbuffered external reference, 2.2 v 2 5 v eref+ = 1.5 v srefx = 010, unbuffered external reference, 3 v 2 5 v eref+ = 2.5 v e t total unadjusted error lsb srefx = 011, buffered external reference (1) , 2.2 v 2 7 v eref+ = 1.5 v srefx = 011, buffered external reference (1) , 3 v 2 6 v eref+ = 2.5 v (1) the reference buffer offset adds to the gain and total unadjusted error. 10-bit adc, temperature sensor and built-in v mid (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit 2.2 v 40 120 temperature sensor supply refon = 0, inchx = 0ah, i sensor a current (1) t a = 25 c 3 v 60 160 tc sensor adc10on = 1, inchx = 0ah (2) 2.2 v, 3 v 3.44 3.55 3.66 mv/ c v offset,sensor sensor offset voltage adc10on = 1, inchx = 0ah (2) -100 100 mv temperature sensor voltage at 1265 1365 1465 t a = 105 c (t version only) temperature sensor voltage at t a = 85 c 1195 1295 1395 v sensor sensor output voltage (3) 2.2 v, 3 v mv temperature sensor voltage at t a = 25 c 985 1085 1185 temperature sensor voltage at t a = 0 c 895 995 1095 sample time required if adc10on = 1, inchx = 0ah, t sensor(sample) 2.2 v, 3 v 30 s channel 10 is selected (4) error of conversion result 1 lsb 2.2 v n/a current into divider at i vmid adc10on = 1, inchx = 0bh a channel 11 (4) 3 v n/a 2.2 v 1.06 1.1 1.14 adc10on = 1, inchx = 0bh, v mid v cc divider at channel 11 v v mid 0.5 v cc 3 v 1.46 1.5 1.54 2.2 v 1400 sample time required if adc10on = 1, inchx = 0bh, t vmid(sample) ns channel 11 is selected (5) error of conversion result 1 lsb 3 v 1220 (1) the sensor current i sensor is consumed if (adc10on = 1 and refon = 1), or (adc10on = 1 and inch = 0ah and sample signal is high).when refon = 1, i sensor is included in i ref+ .when refon = 0, i sensor applies during conversion of the temperature sensor input (inch = 0ah). (2) the following formula can be used to calculate the temperature sensor output voltage: v sensor,typ = tc sensor ( 273 + t [ c] ) + v offset,sensor [mv] or v sensor,typ = tc sensor t [ c] + v sensor (t a = 0 c) [mv] (3) results based on characterization and/or production test, not tc sensor or v offset,sensor . (4) no additional current is needed. the v mid is used during sampling. (5) the on time, t vmid(on) , is included in the sampling time, t vmid(sample) ; no additional on time is needed. copyright ? 2006 ? 2012, texas instruments incorporated 51
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com operational amplifier (oa) supply specifications (msp430f22x4 only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit v cc supply voltage range 2.2 3.6 v fast mode 180 290 i cc supply current (1) medium mode 2.2 v, 3 v 110 190 a slow mode 50 80 psrr power-supply rejection ratio noninverting 2.2 v, 3 v 70 db (1) corresponding pins configured as oa inputs and outputs, respectively. operational amplifier (oa) input/output specifications (msp430f22x4 only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit v i/p input voltage range -0.1 v cc - 1.2 v t a = -40 to +55 c -5 0.5 5 input leakage i lkg t a = +55 to +85 c 2.2 v, 3 v -20 5 20 na current (1) (2) t a = +85 to +105 c -50 50 fast mode 50 medium mode f v(i/p) = 1 khz 80 slow mode 140 voltage noise v n nv/ hz density, i/p fast mode 30 medium mode f v(i/p) = 10 khz 50 slow mode 65 v io offset voltage, i/p 2.2 v, 3 v 10 mv offset temperature 2.2 v, 3 v 10 v/ c drift, i/p (3) offset voltage drift 0.3 v v in v cc - 1.0 v 2.2 v, 3 v 1.5 mv/v with supply, i/p v cc 10%, t a = 25 c fast mode, i source -500 a v cc - 0.2 v cc high-level output v oh 2.2 v, 3 v v voltage, o/p slow mode, i source -150 a v cc - 0.1 v cc fast mode, i source 500 a v ss 0.2 low-level output v ol 2.2 v, 3 v v voltage, o/p slow mode, i source 150 a v ss 0.1 r load = 3 k ? , c load = 50 pf, 150 250 v o/p(oax) < 0.2 v output resistance (4) r load = 3 k ? , c load = 50 pf, r o/p(oax) 2.2 v, 3 v 150 250 ? (see figure 25 ) v o/p(oax) > v cc - 1.2 v r load = 3 k ? , c load = 50 pf, 0.1 4 0.2 v v o/p(oax) v cc - 0.2 v common-mode cmrr noninverting 2.2 v, 3 v 70 db rejection ratio (1) esd damage can degrade input current leakage. (2) the input bias current is overridden by the input leakage current. (3) calculated using the box method (4) specification valid for voltage-follower oax configuration 52 copyright ? 2006 ? 2012, texas instruments incorporated
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 figure 25. oax output resistance tests operational amplifier (oa) dynamic specifications (msp430f22x4 only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit fast mode 1.2 sr slew rate medium mode 0.8 v/ s slow mode 0.3 open-loop voltage gain 100 db m phase margin c l = 50 pf 60 deg gain margin c l = 50 pf 20 db noninverting, fast mode, 2.2 r l = 47 k ? , c l = 50 pf gain-bandwidth product noninverting, medium mode, gbw 2.2 v, 3 v 1.4 mhz (see figure 26 and figure 27 ) r l = 300 k ? , c l = 50 pf noninverting, slow mode, 0.5 r l = 300 k ? , c l = 50 pf t en(on) enable time on t on , noninverting, gain = 1 2.2 v, 3 v 10 20 s t en(off) enable time off 2.2 v, 3 v 1 s typical open-loop gain typical phase vs vs frequency frequency figure 26. figure 27. copyright ? 2006 ? 2012, texas instruments incorporated 53 input frequency ? khz ?250 ?200 ?150 ?100 ?50 0 1 10 100 1000 10000 100000 phase ? degrees slow mode fast mode medium mode input frequency ? khz ?80 ?60 ?40 ?20 0 20 40 60 80 100 120 140 1 10 100 1000 10000 100000 slow mode fast mode gain ? db medium mode r o/p(oax) max 0.2v av cc av cc ?0.2v v out min r load av cc c load 2 i load oax o/p(oax)
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com operational amplifier oa feedback network, resistor network (msp430f22x4 only) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit r total total resistance of resistor string 76 96 128 k ? r unit unit resistor of resistor string (2) 4.8 6 8 k ? (1) a single resistor string is composed of 4 r unit + 4 r unit + 2 r unit + 2 r unit + 1 r unit + 1 r unit + 1 r unit + 1 r unit = 16 r unit = r total . (2) for the matching (that is, the relative accuracy) of the unit resistors on a device, see the gain and level specifications of the respective configurations. operational amplifier (oa) feedback network, comparator mode (oafcx = 3) (msp430f22x4 only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit oafbrx = 1, oarrip = 0 0.245 0.25 0.255 oafbrx = 2, oarrip = 0 0.495 0.5 0.505 oafbrx = 3, oarrip = 0 0.619 0.625 0.631 oafbrx = 4, oarrip = 0 n/a (1) oafbrx = 5, oarrip = 0 n/a (1) oafbrx = 6, oarrip = 0 n/a (1) oafbrx = 7, oarrip = 0 n/a (1) v level comparator level 2.2 v, 3 v v cc oafbrx = 1, oarrip = 1 0.061 0.0625 0.065 oafbrx = 2, oarrip = 1 0.122 0.125 0.128 oafbrx = 3, oarrip = 1 0.184 0.1875 0.192 oafbrx = 4, oarrip = 1 0.245 0.25 0.255 oafbrx = 5, oarrip = 1 0.367 0.375 0.383 oafbrx = 6, oarrip = 1 0.495 0.5 0.505 oafbrx = 7, oarrip = 1 n/a (1) fast mode, overdrive 10 mv 40 fast mode, overdrive 100 mv 4 fast mode, overdrive 500 mv 3 medium mode, overdrive 10 mv 60 t plh , propagation delay medium mode, overdrive 100 mv 2.2 v, 3 v 6 s t phl (low-high and high-low) medium mode, overdrive 500 mv 5 slow mode, overdrive 10 mv 160 slow mode, overdrive 100 mv 20 slow mode, overdrive 500 mv 15 (1) the level is not available due to the analog input voltage range of the operational amplifier. 54 copyright ? 2006 ? 2012, texas instruments incorporated
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 operational amplifier (oa) feedback network, noninverting amplifier mode (oafcx = 4) (msp430f22x4 only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit oafbrx = 0 0.998 1 1.002 oafbrx = 1 1.328 1.334 1.340 oafbrx = 2 1.985 2.001 2.017 oafbrx = 3 2.638 2.667 2.696 g gain 2.2 v, 3 v oafbrx = 4 3.94 4 4.06 oafbrx = 5 5.22 5.33 5.44 oafbrx = 6 7.76 7.97 8.18 oafbrx = 7 15 15.8 16.6 2.2 v -60 thd total harmonic distortion/nonlinearity all gains db 3 v -70 t settle settling time (1) all power modes 2.2 v, 3 v 7 12 s (1) the settling time specifies the time until an adc result is stable. this includes the minimum required sampling time of the adc. the settling time of the amplifier itself might be faster. operational amplifier (oa) feedback network, inverting amplifier mode (oafcx = 6) (msp430f22x4 only) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit oafbrx = 1 -0.345 -0.335 -0.325 oafbrx = 2 -1.023 -1.002 -0.979 oafbrx = 3 -1.712 -1.668 -1.624 g gain oafbrx = 4 2.2 v, 3 v -3.1 -3 -2.9 oafbrx = 5 -4.51 -4.33 -4.15 oafbrx = 6 -7.37 -6.97 -6.57 oafbrx = 7 -16.3 -14.8 -13.1 2.2 v -60 thd total harmonic distortion/nonlinearity all gains db 3 v -70 t settle settling time (2) all power modes 2.2 v, 3 v 7 12 s (1) this includes the 2 oa configuration " inverting amplifier with input buffer " . both oa needs to be set to the same power mode oapmx. (2) the settling time specifies the time until an adc result is stable. this includes the minimum required sampling time of the adc. the settling time of the amplifier itself might be faster. copyright ? 2006 ? 2012, texas instruments incorporated 55
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com flash memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit v cc (pgm/erase) program and erase supply voltage 2.2 3.6 v f ftg flash timing generator frequency 257 476 khz i pgm supply current from v cc during program 2.2 v, 3.6 v 1 5 ma i erase supply current from v cc during erase 2.2 v, 3.6 v 1 7 ma t cpt cumulative program time (1) 2.2 v, 3.6 v 10 ms t cmerase cumulative mass erase time 2.2 v, 3.6 v 20 ms program/erase endurance 10 4 10 5 cycles t retention data retention duration t j = 25 c 100 years t word word or byte program time (2) 30 t ftg t block, 0 block program time for first byte or word (2) 25 t ftg block program time for each additional t block, 1-63 (2) 18 t ftg byte or word t block, end block program end-sequence wait time (2) 6 t ftg t mass erase mass erase time (2) 10593 t ftg t seg erase segment erase time (2) 4819 t ftg (1) the cumulative program time must not be exceeded when writing to a 64-byte flash block. this parameter applies to all programming methods: individual word/byte write and block write modes. (2) these values are hardwired into the flash controller ' s state machine (t ftg = 1/f ftg ). ram over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min max unit v (ramh) ram retention supply voltage (1) cpu halted 1.6 v (1) this parameter defines the minimum supply voltage v cc when the data in ram remains unchanged. no program execution should happen during this supply voltage condition. 56 copyright ? 2006 ? 2012, texas instruments incorporated
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 jtag and spy-bi-wire interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit f sbw spy-bi-wire input frequency 2.2 v, 3 v 0 20 mhz t sbw,low spy-bi-wire low clock pulse length 2.2 v, 3 v 0.025 15 s spy-bi-wire enable time t sbw,en 2.2 v, 3 v 1 s (test high to acceptance of first clock edge (1) ) t sbw,ret spy-bi-wire return to normal operation time 2.2 v, 3 v 15 100 s 2.2 v 0 5 mhz f tck tck input frequency (2) 3 v 0 10 mhz r internal internal pulldown resistance on test 2.2 v, 3 v 25 60 90 k ? (1) tools accessing the spy-bi-wire interface need to wait for the maximum t sbw,en time after pulling the test/sbwclk pin high before applying the first sbwclk clock edge. (2) f tck may be restricted to meet the timing requirements of the module selected. jtag fuse (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min max unit v cc(fb) supply voltage during fuse-blow condition t a = 25 c 2.5 v v fb voltage level on test for fuse blow 6 7 v i fb supply current into test during fuse blow 100 ma t fb time to blow fuse 1 ms (1) once the fuse is blown, no further access to the jtag/test, spy-bi-wire, and emulation feature is possible, and jtag is switched to bypass mode. copyright ? 2006 ? 2012, texas instruments incorporated 57
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com application information port p1 pin schematic: p1.0 to p1.3, input/output with schmitt trigger table 21. port p1 (p1.0 to p1.3) pin functions control bits/signals pin name (p1.x) x function p1dir.x p1sel.x p1.0 (1) i: 0; o: 1 0 p1.0/taclk/adc10clk 0 timer_a3.taclk 0 1 adc10clk 1 1 p1.1 (1) (i/o) i: 0; o: 1 0 p1.1/ta0 1 timer_a3.cci0a 0 1 timer_a3.ta0 1 1 p1.2 (1) (i/o) i: 0; o: 1 0 p1.2/ta1 2 timer_a3.cci1a 0 1 timer_a3.ta1 1 1 p1.3 (1) (i/o) i: 0; o: 1 0 p1.3/ta2 3 timer_a3.cci2a 0 1 timer_a3.ta2 1 1 (1) default after reset (puc/por) 58 copyright ? 2006 ? 2012, texas instruments incorporated direction 0: input 1: output p1sel.x 1 0 p1dir.x p1in.x p1irq.x d en module x in 1 0 module x out p1out.x interrupt edge select q en set p1sel.x p1ies.x p1ifg.x p1ie.x p1.0/taclk/adc10clk p1.1/ta0 p1.2/ta1 p1.3/ta2 1 0 dvss dvcc p1ren.x pad logic 1
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 port p1 pin schematic: p1.4 to p1.6, input/output with schmitt trigger and in-system access features table 22. port p1 (p1.4 to p1.6) pin functions control bits/signals (1) pin name (p1.x) x function p1dir.x p1sel.x 4-wire jtag p1.4 (2) (i/o) i: 0; o: 1 0 0 p1.4/smclk/tck 4 smclk 1 1 0 tck x x 1 p1.5 (2) (i/o) i: 0; o: 1 0 0 p1.5/ta0/tms 5 timer_a3.ta0 1 1 0 tms x x 1 p1.6 (2) (i/o) i: 0; o: 1 0 0 p1.6/ta1/tdi/tclk 6 timer_a3.ta1 1 1 0 tdi/tclk (3) x x 1 (1) x = don ' t care (2) default after reset (puc/por) (3) function controlled by jtag copyright ? 2006 ? 2012, texas instruments incorporated 59 bus keeper en direction 0: input 1: output p1sel.x 1 0 p1dir.x p1in.x p1irq.x d en module x in 1 0 module x out p1out.x interrupt edge select q en set p1sel.x p1ies.x p1ifg.x p1ie.x p1.4/smclk/tck p1.5/ta0/tms p1.6/ta1/tdi 1 0 dvss dvcc p1ren.x to jtag from jtag 1 pad logic
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com port p1 pin schematic: p1.7, input/output with schmitt trigger and in-system access features table 23. port p1 (p1.7) pin functions control bits/signals (1) pin name (p1.x) x function p1dir.x p1sel.x 4-wire jtag p1.7 (2) (i/o) i: 0; o: 1 0 0 p1.7/ta2/tdo/tdi 7 timer_a3.ta2 1 1 0 tdo/tdi (3) x x 1 (1) x = don ' t care (2) default after reset (puc/por) (3) function controlled by jtag 60 copyright ? 2006 ? 2012, texas instruments incorporated from jtag from jtag (tdo) bus keeper en direction 0: input 1: output p1sel.7 1 0 p1dir.7 p1in.7 p1irq.7 d en module x in 1 0 module x out p1out.7 interrupt edge select q en set p1sel.7 p1ies.7 p1ifg.7 p1ie.7 p1.7/ta2/tdo/tdi 1 0 dvss dvcc p1ren.7 to jtag from jtag 1 pad logic
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 port p2 pin schematic: p2.0, p2.2, input/output with schmitt trigger table 24. port p2 (p2.0, p2.2) pin functions control bits/signals (1) pin name (p2.x) x y function p2dir.x p2sel.x adc10ae0.y p2.0 (2) (i/o) i: 0; o: 1 0 0 p2.0/aclk/a0/oa0i0 0 0 aclk 1 1 0 a0/oa0i0 (3) x x 1 p2.2 (2) (i/o) i: 0; o: 1 0 0 timer_a3.cci0b 0 1 0 p2.2/ta0/a2/oa0i1 2 2 timer_a3.ta0 1 1 0 a2/oa0i1 (3) x x 1 (1) x = don ' t care (2) default after reset (puc/por) (3) setting the adc10ae0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. copyright ? 2006 ? 2012, texas instruments incorporated 61 bus keeper en direction 0: input 1: output p2sel.x 1 0 p2dir.x p2in.x p2irq.x d en module x in 1 0 module x out p2out.x interrupt edge select q en set p2sel.x p2ies.x p2ifg.x p2ie.x p2.0/aclk/a0/oa0i0 p2.2/ta0/a2/oa0i1 1 0 dvss dvcc p2ren.x adc10ae0.y pad logic inchx = y to adc 10 1 oa0 + ?
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com port p2 pin schematic: p2.1, input/output with schmitt trigger table 25. port p2 (p2.1) pin functions control bits/signals (1) pin name (p2.x) x y function p2dir.x p2sel.x adc10ae0.y p2.1 (2) (i/o) i: 0; o: 1 0 0 timer_a3.inclk 0 1 0 p2.1/tainclk/smclk/ 1 1 a1/oa0o smclk 1 1 0 a1/oa0o (3) x x 1 (1) x = don ' t care (2) default after reset (puc/por) (3) setting the adc10ae0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. 62 copyright ? 2006 ? 2012, texas instruments incorporated 1 oafcx oapmx oaadcx to oa0 feedback network 1 (oaadcx = 10 or oafcx = 000) and oapmx > 00 bus keeper en direction 0: input 1: output p2sel.1 1 0 p2dir.1 p2in.1 p2irq.1 d en module x in 1 0 module x out p2out.1 interrupt edge select q en set p2sel.1 p2ies.1 p2ifg.1 p2ie.1 p2.1/tainclk/smclk/ a1/oa0o 1 0 dvssdvcc p2ren.1 adc10ae0.1 pad logic inchx = 1 to adc 10 1 oa0 + ? 1
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 port p2 pin schematic: p2.3, input/output with schmitt trigger copyright ? 2006 ? 2012, texas instruments incorporated 63 bus keeper en direction 0: input 1: output p2sel.3 1 0 p2dir.3 p2in.3 p2irq.3 d en module x in 1 0 module x out p2out.3 interrupt edge select q en set p2sel.3 p2ies.3 p2ifg.3 p2ie.3 1 0 dvss dvcc p2ren.3 adc10ae0.3 pad logic inchx = 3 to adc 10 1 oa1 + ? 1 oafcx oapmx oaadcx to oa1 feedback network to adc 10 v r? 1 0 sref2 vss p2.3/ta1/ a3/vref?/veref?/ oa1i1/oa1o 1 (oaadcx = 10 or oafcx = 000) and oapmx > 00
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com table 26. port p2 (p2.3) pin functions control bits/signals (1) pin name (p2.x) x y function p2dir.x p2sel.x adc10ae0.y p2.3 (2) (i/o) i: 0; o: 1 0 0 timer_a3.cci1b 0 1 0 p2.3/ta1/a3/v ref- 3 3 /v eref- / oa1i1/oa1o timer_a3.ta1 1 1 0 a3/v ref- /v eref- /oa1i1/oa1o (3) x x 1 (1) x = don ' t care (2) default after reset (puc/por) (3) setting the adc10ae0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. 64 copyright ? 2006 ? 2012, texas instruments incorporated
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 port p2 pin schematic: p2.4, input/output with schmitt trigger table 27. port p2 (p2.4) pin functions control bits/signals (1) pin name (p2.x) x y function p2dir.x p2sel.x adc10ae0.y p2.4 (2) (i/o) i: 0; o: 1 0 0 p2.4/ta2/a4/v ref+ / 4 4 timer_a3.ta2 1 1 0 v eref+ / oa1i0 a4/v ref+ /v eref+ /oa1i0 (3) x x 1 (1) x = don ' t care (2) default after reset (puc/por) (3) setting the adc10ae0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. copyright ? 2006 ? 2012, texas instruments incorporated 65 bus keeper en direction 0: input 1: output p2sel.4 1 0 p2dir.4 p2in.4 p2irq.4 d en module x in 1 0 module x out p2out.4 interrupt edge select q en set p2sel.4 p2ies.4 p2ifg.4 p2ie.4 p2.4/ta2/ a4/vref+/veref+/ oa1i0 1 0 dvss dvcc p2ren.4 adc10ae0.4 pad logic inchx = 4 to adc 10 1 to /from adc10 positive reference oa1 + ?
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com port p2 pin schematic: p2.5, input/output with schmitt trigger and external r osc for dco table 28. port p2 (p2.5) pin functions control bits/signals (1) pin name (p2.x) x function p2dir.x p2sel.x dcor p2.5 (2) (i/o) i: 0; o: 1 0 0 n/a (3) 0 1 0 p2.5/r osc 5 dv ss 1 1 0 r osc x x 1 (1) x = don ' t care (2) default after reset (puc/por) (3) n/a = not available or not applicable 66 copyright ? 2006 ? 2012, texas instruments incorporated bus keeper en direction 0: input 1: output p2sel.x 1 0 p2dir.x p2in.x p2irq.x d en module x in 1 0 module x out p2out.x interrupt edge select q en set p2sel.x p2ies.x p2ifg.x p2ie.x p2.5/rosc 1 0 dvss dvcc p2ren.x dcor pad logic to dco 1
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 port p2 pin schematic: p2.6, input/output with schmitt trigger and crystal oscillator input table 29. port p2 (p2.6) pin functions control bits/signals (1) pin name (p2.x) x function p2dir.x p2sel.x p2.6 (i/o) i: 0; o: 1 0 p2.6/xin 6 xin (2) x 1 (1) x = don ' t care (2) default after reset (puc/por) copyright ? 2006 ? 2012, texas instruments incorporated 67 lfxt1 off p2sel.7 bus keeper en direction 0: input 1: output p2sel.6 1 0 p2dir.6 p2in.6 p2irq.6 d en module x in 1 0 module x out p2out.6 interrupt edge select q en set p2sel.6 p2ies.6 p2ifg.6 p2ie.6 p2.6/xin 1 0 dvss dvcc p2ren.6 pad logic lfxt1 oscillator bcsctl3.lfxt1sx = 11 p2.7/xout 01 1 lfxt1clk
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com port p2 pin schematic: p2.7, input/output with schmitt trigger and crystal oscillator output table 30. port p2 (p2.7) pin functions control bits/signals (1) pin name (p2.x) x function p2dir.x p2sel.x p2.7 (i/o) i: 0; o: 1 0 xout/p2.7 7 xout (2) (3) x 1 (1) x = don ' t care (2) default after reset (puc/por) (3) if the pin xout/p2.7 is used as an input a current can flow until p2sel.7 is cleared due to the oscillator output driver connection to this pin after reset. 68 copyright ? 2006 ? 2012, texas instruments incorporated lfxt1 off p2sel.6 bus keeper en direction 0: input 1: output p2sel.7 1 0 p2dir.7 p2in.7 p2irq.7 d en module x in 1 0 module x out p2out.7 interrupt edge select q en set p2sel.7 p2ies.7 p2ifg.7 p2ie.7 p2.7/xout 1 0 dvss dvcc p2ren.7 pad logic lfxt1 oscillator bcsctl3.lfxt1sx = 11 01 1 lfxt1clk from p2.6/xin p2.6/xin
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 port p3 pin schematic: p3.0, input/output with schmitt trigger table 31. port p3 (p3.0) pin functions control bits/signals (1) pin name (p1.x) x y function p3dir.x p3sel.x adc10ae0.y p3.0 (2) (i/o) i: 0; o: 1 0 0 p3.0/ucb0ste/ 0 5 ucb0ste/uca0clk (3) (4) x 1 0 uca0clk/a5 a5 (5) x x 1 (1) x = don ' t care (2) default after reset (puc/por) (3) the pin direction is controlled by the usci module. (4) uca0clk function takes precedence over ucb0ste function. if the pin is required as uca0clk input or output, usci_b0 is forced to 3-wire spi mode if 4-wire spi mode is selected. (5) setting the adc10ae0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. copyright ? 2006 ? 2012, texas instruments incorporated 69 bus keeper en direction 0: input 1: output p3sel.0 1 0 p3dir.0 p3in.0 d en module x in 1 0 module x out p3out.0 1 0 dvss dvcc p3ren.0 adc10ae0.5 pad logic inchx = 5 to adc 10 1 usci direction control p3.0/ucb0ste/uca0clk/a5
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com port p3 pin schematic: p3.1 to p3.5, input/output with schmitt trigger table 32. port p3 (p3.1 to p3.5) pin functions control bits/signals (1) pin name (p3.x) x function p3dir.x p3sel.x p3.1 (2) (i/o) i: 0; o: 1 0 p3.1/ucb0simo/ucb0sda 1 ucb0simo/ucb0sda (3) x 1 p3.2 (2) (i/o) i: 0; o: 1 0 p3.2/ucb0somi/ucb0scl 2 ucb0somi/ucb0scl (3) x 1 p3.3 (2) (i/o) i: 0; o: 1 0 p3.3/ucb0clk/uca0ste 3 ucb0clk/uca0ste (3) (4) x 1 p3.4 (2) (i/o) i: 0; o: 1 0 p3.4/uca0txd/uca0simo 4 uca0txd/uca0simo (3) x 1 p3.5 (2) (i/o) i: 0; o: 1 0 p3.5/uca0rxd/uca0somi 5 uca0rxd/uca0somi (3) x 1 (1) x = don ' t care (2) default after reset (puc/por) (3) the pin direction is controlled by the usci module. (4) ucb0clk function takes precedence over uca0ste function. if the pin is required as ucb0clk input or output, usci_a0 is forced to 3-wire spi mode even if 4-wire spi mode is selected. 70 copyright ? 2006 ? 2012, texas instruments incorporated bus keeper en direction 0: input 1: output p3sel.x 1 0 p3dir.x p3in.x d en module x in 1 0 module x out p3out.x 1 0 dvssdvcc p3ren.x pad logic 1 usci direction control dvss p3.1/ucb0simo/ucb0sdap3.2/ucb0somi/ucb0scl p3.3/ucb0clk/uca0ste p3.4/uca0txd/uca0simo p3.5/uca0rxd/uca0somi
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 port p3 pin schematic: p3.6 to p3.7, input/output with schmitt trigger table 33. port p3 (p3.6, p3.7) pin functions control bits/signals (1) pin name (p3.x) x y function p3dir.x p3sel.x adc10ae0.y p3.6 (2) (i/o) i: 0; o: 1 0 0 p3.6/a6/oa0i2 6 6 a6/oa0i2 (3) x x 1 p3.7 (2) (i/o) i: 0; o: 1 0 0 p3.7/a7/oa1i2 7 7 a7/oa1i2 (3) x x 1 (1) x = don ' t care (2) default after reset (puc/por) (3) setting the adc10ae0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. copyright ? 2006 ? 2012, texas instruments incorporated 71 bus keeper en direction 0: input 1: output p3sel.x 1 0 p3dir.x p3in.x d en module x in 1 0 module x out p3out.x p3.6/a6/oa0i2 p3.7/a7/oa1i2 1 0 dvssdvcc p3ren.x adc10ae0.y pad logic inchx = y to adc 10 1 oa0/1 + ? dvss
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com port p4 pin schematic: p4.0 to p4.2, input/output with schmitt trigger table 34. port p4 (p4.0 to p4.2) pin functions control bits/signals pin name (p4.x) x function p4dir.x p4sel.x p4.0 (1) (i/o) i: 0; o: 1 0 p4.0/tb0 0 timer_b3.cci0a 0 1 timer_b3.tb0 1 1 p4.1 (1) (i/o) i: 0; o: 1 0 p4.1/tb1 1 timer_b3.cci1a 0 1 timer_b3.tb1 1 1 p4.2 (1) (i/o) i: 0; o: 1 0 p4.2/tb2 2 timer_b3.cci2a 0 1 timer_b3.tb2 1 1 (1) default after reset (puc/por) 72 copyright ? 2006 ? 2012, texas instruments incorporated bus keeper en direction 0: input 1: output p4sel.x 1 0 p4dir.x p4in.x d en module x in 1 0 module x out p4out.x p4.0/tb0 p4.1/tb1 p4.2/tb2 1 0 dvss dvcc p4ren.x pad logic 1 p4dir.6 p4sel.6 adc10ae1.7 p4.6/tbouth/a15/oa1i3 timer_b output tristate logic
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 port p4 pin schematic: p4.3 to p4.4, input/output with schmitt trigger ? if oaadcx = 11 and not oafcx = 000, the adc input a12 or a13 is internally connected to the oa0 or oa1 output, respectively, and the connections from the adc and the operational amplifiers to the pad are disabled. copyright ? 2006 ? 2012, texas instruments incorporated 73 oapmx oaadcx to oa0/1 feedback network 1 oaadcx = 01 and oapmx > 00 bus keeper en direction 0: input 1: output p4sel.x 1 0 p4dir.x p4in.x d en module x in 1 0 module x out p4out.x p4.3/tb0/a12/oa0o p4.4/tb1/a13/oa1o 1 0 dvss dvcc p4ren.x adc10ae1.y pad logic inchx = 8+y to adc 10 1 oa0/1 + ? 1 p4dir.6 p4sel.6 adc10ae1.7 p4.6/tbouth/a15/oa1i3 timer_b output tristate logic ?
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com table 35. port p4 (p4.3 to p4.4) pin functions control bits/signals (1) pin name (p4.x) x y function p4dir.x p4sel.x adc10ae1.y p4.3 (2) (i/o) i: 0; o: 1 0 0 timer_b3.cci0b 0 1 0 p4.3/tb0/a12/oa0o 3 4 timer_b3.tb0 1 1 0 a12/oa0o (3) x x 1 p4.4 (2) (i/o) i: 0; o: 1 0 0 timer_b3.cci1b 0 1 0 p4.4/tb1/a13/oa1o 4 5 timer_b3.tb1 1 1 0 a13/oa1o (3) x x 1 (1) x = don ' t care (2) default after reset (puc/por) (3) setting the adc10ae1.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. 74 copyright ? 2006 ? 2012, texas instruments incorporated
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 port p4 pin schematic: p4.5, input/output with schmitt trigger table 36. port p4 (p4.5) pin functions control bits/signals (1) pin name (p4.x) x y function p4dir.x p4sel.x adc10ae1.y p4.5 (2) (i/o) i: 0; o: 1 0 0 p4.5/tb3/a14/oa0i3 5 6 timer_b3.tb2 1 1 0 a14/oa0i3 (3) x x 1 (1) x = don ' t care (2) default after reset (puc/por) (3) setting the adc10ae1.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. copyright ? 2006 ? 2012, texas instruments incorporated 75 bus keeper en direction 0: input 1: output p4sel.5 1 0 p4dir.5 p4in.5 d en module x in 1 0 module x out p4out.5 p4.5/tb3/a14/oa0i3 1 0 dvss dvcc p4ren.5 adc10ae1.6 pad logic inchx = 14 to adc 10 1 p4dir.6 p4sel.6 adc10ae1.7 p4.6/tbouth/a15/oa1i3 timer_b output tristate logic oa0 + ?
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com port p4 pin schematic: p4.6, input/output with schmitt trigger table 37. port p4 (p4.6) pin functions control bits/signals (1) pin name (p4.x) x y function p4dir.x p4sel.x adc10ae1.y p4.6 (2) (i/o) i: 0; o: 1 0 0 tbouth 0 1 0 p4.6/tbouth/a15/oa1i3 6 7 dv ss 1 1 0 a15/oa1i3 (3) x x 1 (1) x = don ' t care (2) default after reset (puc/por) (3) setting the adc10ae1.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. 76 copyright ? 2006 ? 2012, texas instruments incorporated bus keeper en direction 0: input 1: output p4sel.6 1 0 p4dir.6 p4in.6 d en module x in 1 0 module x out p4out.6 1 0 dvss dvcc p4ren.6 adc10ae1.7 pad logic inchx = 15 to adc 10 1 oa1 + ? p4.6/tbouth/ a15/oa1i3
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 port p4 pin schematic: p4.7, input/output with schmitt trigger table 38. port p4 (pr.7) pin functions control bits/signals pin name (p4.x) x function p4dir.x p4sel.x p4.7 (1) (i/o) i: 0; o: 1 0 p4.7/tbclk 7 timer_b3.tbclk 0 1 dv ss 1 1 (1) default after reset (puc/por) copyright ? 2006 ? 2012, texas instruments incorporated 77 bus keeper en direction 0: input 1: output p4sel.x 1 0 p4dir.x p4in.x d en module x in 1 0 module x out p4out.x p4.7/tbclk 1 0 dvssdvcc p4ren.x pad logic 1 dvss
msp430f22x2 msp430f22x4 slas504g ? july 2006 ? revised august 2012 www.ti.com jtag fuse check mode msp430 devices that have the fuse on the test terminal have a fuse check mode that tests the continuity of the fuse the first time the jtag port is accessed after a power-on reset (por). when activated, a fuse check current, i tf , of 1 ma at 3 v, 2.5 ma at 5 v can flow from the test pin to ground if the fuse is not burned. care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. when the test pin is again taken low after a test or programming session, the fuse check mode and sense currents are terminated. activation of the fuse check mode occurs with the first negative edge on the tms pin after power up or if tms is being held low during power up. the second positive edge on the tms pin deactivates the fuse check mode. after deactivation, the fuse check mode remains inactive until another por occurs. after each por the fuse check mode has the potential to be activated. the fuse check current flows only when the fuse check mode is active and the tms pin is in a low state (see figure 28 ). therefore, the additional current flow can be prevented by holding the tms pin high (default condition). figure 28. fuse check mode current note the code and ram data protection is ensured if the jtag fuse is blown and the 256-bit bootloader access key is used. also, see the bootstrap loader section for more information. 78 copyright ? 2006 ? 2012, texas instruments incorporated time tms goes low after por tms i tf i test
msp430f22x2 msp430f22x4 www.ti.com slas504g ? july 2006 ? revised august 2012 revision history literature summary number slas504 preliminary data sheet release slas504a production data sheet release updated specification and added characterization graphs updated/corrected port pin schematics slas504b maximum low-power mode supply current limits decreased added note concerning f ucxclk to usci spi parameters slas504c added development tool support section (page 2) changed t stg for programmed devices from " -40 c to 105 c " to " -55 c to 105 c " (page 23) slas504d corrected pin names in " port p3 pin schematic: p3.0 " and " port p3 (p3.0) pin functions " (page 68) corrected pin names in " port p3 pin schematic: p3.1 to p3.5 " and " port p3 (p3.1 to p3.5) pin functions " (page 69) corrected signal names in " port p2 pin schematic: p2.5, input/output " (page 65) (d1) corrected values in " x " column in " port p3 (p3.1 to p3.5) pin functions " (page 69) (d2) slas504e added information for yff package slas504f correct signal names for p3.6 and p3.7 in msp430f22x2 pinouts ? da package , rha package changed storage temperature range limit in absolute maximum ratings corrected test conditions in crystal oscillator lfxt1, high-frequency mode corrected signal names in port p1 (p1.0 to p1.3) pin functions corrected typo in note 1 on crystal oscillator lfxt1, high-frequency mode table slas504g terminal functions tables, corrected description of v ref- /v eref- pins. added note on tc ref+ in 10-bit adc, built-in voltage reference . copyright ? 2006 ? 2012, texas instruments incorporated 79
package option addendum www.ti.com 15-apr-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples msp430a061idar active tssop da 38 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 m430f2252 msp430a142irhar active vqfn rha 40 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430 f2272 MSP430A150IDAR active tssop da 38 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 m430f2254 msp430f2232ida active tssop da 38 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 m430f2232 msp430f2232idar active tssop da 38 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 m430f2232 msp430f2232irhar active vqfn rha 40 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430 f2232 msp430f2232irhat active vqfn rha 40 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430 f2232 msp430f2232iyffr active dsbga yff 49 2500 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 m430f2232 msp430f2232tda active tssop da 38 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 105 m430f2232t msp430f2232tdar active tssop da 38 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 105 m430f2232t msp430f2232trhar active vqfn rha 40 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 m430 f2232t msp430f2232trhat active vqfn rha 40 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 m430 f2232t msp430f2234ida active tssop da 38 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 m430f2234 msp430f2234idar active tssop da 38 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 m430f2234 msp430f2234irhar active vqfn rha 40 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430 f2234 msp430f2234irhat active vqfn rha 40 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430 f2234 msp430f2234iyffr active dsbga yff 49 2500 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 m430f2234
package option addendum www.ti.com 15-apr-2017 addendum-page 2 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples msp430f2234tda active tssop da 38 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 105 m430f2234t msp430f2234tdar active tssop da 38 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 105 m430f2234t msp430f2234trhar active vqfn rha 40 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 m430 f2234t msp430f2234trhat active vqfn rha 40 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 m430 f2234t msp430f2252ida active tssop da 38 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 m430f2252 msp430f2252idar active tssop da 38 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 m430f2252 msp430f2252irhar active vqfn rha 40 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430 f2252 msp430f2252irhat active vqfn rha 40 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430 f2252 msp430f2252iyffr active dsbga yff 49 2500 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 m430f2252 msp430f2252tda active tssop da 38 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 105 m430f2252t msp430f2252tdar active tssop da 38 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 105 m430f2252t msp430f2252trhar active vqfn rha 40 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 m430 f2252t msp430f2252trhat active vqfn rha 40 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 m430 f2252t msp430f2254ida active tssop da 38 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 m430f2254 msp430f2254idar active tssop da 38 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 m430f2254 msp430f2254irhar active vqfn rha 40 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430 f2254 msp430f2254irhat active vqfn rha 40 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430 f2254 msp430f2254iyffr active dsbga yff 49 2500 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 m430f2254
package option addendum www.ti.com 15-apr-2017 addendum-page 3 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples msp430f2254tda active tssop da 38 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 105 m430f2254t msp430f2254tdar active tssop da 38 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 105 m430f2254t msp430f2254trhar active vqfn rha 40 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 m430 f2254t msp430f2254trhat active vqfn rha 40 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 m430 f2254t msp430f2272ida active tssop da 38 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 m430f2272 msp430f2272idar active tssop da 38 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 m430f2272 msp430f2272irhar active vqfn rha 40 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430 f2272 msp430f2272irhat active vqfn rha 40 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430 f2272 msp430f2272iyffr active dsbga yff 49 2500 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 m430f2272 msp430f2272iyfft active dsbga yff 49 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 m430f2272 msp430f2272tda active tssop da 38 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 105 m430f2272t msp430f2272tdar active tssop da 38 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 105 m430f2272t msp430f2272trhar active vqfn rha 40 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 m430 f2272t msp430f2272trhat active vqfn rha 40 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 m430 f2272t msp430f2274ida active tssop da 38 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 m430f2274 msp430f2274idar active tssop da 38 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 m430f2274 msp430f2274irhar active vqfn rha 40 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430 f2274 msp430f2274irhat active vqfn rha 40 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430 f2274
package option addendum www.ti.com 15-apr-2017 addendum-page 4 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples msp430f2274iyffr active dsbga yff 49 2500 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 m430f2274 msp430f2274iyfft active dsbga yff 49 250 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 m430f2274 msp430f2274tda active tssop da 38 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 105 m430f2274t msp430f2274tdar active tssop da 38 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 105 m430f2274t msp430f2274trhar active vqfn rha 40 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 m430 f2274t msp430f2274trhat active vqfn rha 40 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 m430 f2274t (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device.
package option addendum www.ti.com 15-apr-2017 addendum-page 5 (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of msp430f2252, msp430f2272, msp430f2274 : ? automotive: msp430f2252-q1 , msp430f2272-q1 ? enhanced product: msp430f2274-ep note: qualified version definitions: ? automotive - q100 devices qualified for high-reliability automotive applications targeting zero defects ? enhanced product - supports defense, aerospace and medical applications
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant msp430f2232idar tssop da 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 q1 msp430f2232irhar vqfn rha 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2232irhat vqfn rha 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2232trhar vqfn rha 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2232trhat vqfn rha 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2234idar tssop da 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 q1 msp430f2234irhar vqfn rha 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2234irhat vqfn rha 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2234trhar vqfn rha 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2234trhat vqfn rha 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2252idar tssop da 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 q1 msp430f2252irhar vqfn rha 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2252irhat vqfn rha 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2252trhar vqfn rha 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2252trhat vqfn rha 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2254idar tssop da 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 q1 msp430f2254irhar vqfn rha 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2254irhat vqfn rha 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 package materials information www.ti.com 21-dec-2015 pack materials-page 1
device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant msp430f2254trhar vqfn rha 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2254trhat vqfn rha 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2272idar tssop da 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 q1 msp430f2272irhar vqfn rha 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2272irhat vqfn rha 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2272iyffr dsbga yff 49 2500 330.0 12.4 3.5 3.7 0.81 8.0 12.0 q2 msp430f2272tdar tssop da 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 q1 msp430f2272trhar vqfn rha 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2272trhat vqfn rha 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2274idar tssop da 38 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 q1 msp430f2274irhar vqfn rha 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2274irhat vqfn rha 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2274trhar vqfn rha 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 msp430f2274trhat vqfn rha 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 *all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) msp430f2232idar tssop da 38 2000 367.0 367.0 45.0 msp430f2232irhar vqfn rha 40 2500 367.0 367.0 38.0 msp430f2232irhat vqfn rha 40 250 210.0 185.0 35.0 package materials information www.ti.com 21-dec-2015 pack materials-page 2
device package type package drawing pins spq length (mm) width (mm) height (mm) msp430f2232trhar vqfn rha 40 2500 367.0 367.0 38.0 msp430f2232trhat vqfn rha 40 250 210.0 185.0 35.0 msp430f2234idar tssop da 38 2000 367.0 367.0 45.0 msp430f2234irhar vqfn rha 40 2500 367.0 367.0 38.0 msp430f2234irhat vqfn rha 40 250 210.0 185.0 35.0 msp430f2234trhar vqfn rha 40 2500 367.0 367.0 38.0 msp430f2234trhat vqfn rha 40 250 210.0 185.0 35.0 msp430f2252idar tssop da 38 2000 367.0 367.0 45.0 msp430f2252irhar vqfn rha 40 2500 367.0 367.0 38.0 msp430f2252irhat vqfn rha 40 250 210.0 185.0 35.0 msp430f2252trhar vqfn rha 40 2500 367.0 367.0 38.0 msp430f2252trhat vqfn rha 40 250 210.0 185.0 35.0 msp430f2254idar tssop da 38 2000 367.0 367.0 45.0 msp430f2254irhar vqfn rha 40 2500 367.0 367.0 38.0 msp430f2254irhat vqfn rha 40 250 210.0 185.0 35.0 msp430f2254trhar vqfn rha 40 2500 367.0 367.0 38.0 msp430f2254trhat vqfn rha 40 250 210.0 185.0 35.0 msp430f2272idar tssop da 38 2000 367.0 367.0 45.0 msp430f2272irhar vqfn rha 40 2500 367.0 367.0 38.0 msp430f2272irhat vqfn rha 40 250 210.0 185.0 35.0 msp430f2272iyffr dsbga yff 49 2500 367.0 367.0 35.0 msp430f2272tdar tssop da 38 2000 367.0 367.0 45.0 msp430f2272trhar vqfn rha 40 2500 367.0 367.0 38.0 msp430f2272trhat vqfn rha 40 250 210.0 185.0 35.0 msp430f2274idar tssop da 38 2000 367.0 367.0 45.0 msp430f2274irhar vqfn rha 40 2500 367.0 367.0 38.0 msp430f2274irhat vqfn rha 40 250 210.0 185.0 35.0 msp430f2274trhar vqfn rha 40 2500 367.0 367.0 38.0 msp430f2274trhat vqfn rha 40 250 210.0 185.0 35.0 package materials information www.ti.com 21-dec-2015 pack materials-page 3

d: max = e: max = 3.518 mm, min = 3.36 mm, min = 3.458 mm3.3 mm
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as is ? and with all faults. ti disclaims all other warranties or representations, express or implied, regarding resources or use thereof, including but not limited to accuracy or completeness, title, any epidemic failure warranty and any implied warranties of merchantability, fitness for a particular purpose, and non-infringement of any third party intellectual property rights. ti shall not be liable for and shall not defend or indemnify designer against any claim, including but not limited to any infringement claim that relates to or is based on any combination of products even if described in ti resources or otherwise. in no event shall ti be liable for any actual, direct, special, collateral, indirect, punitive, incidental, consequential or exemplary damages in connection with or arising out of ti resources or use thereof, and regardless of whether ti has been advised of the possibility of such damages. unless ti has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., iso/ts 16949 and iso 26262), ti is not responsible for any failure to meet such industry standard requirements. where ti specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. using products in an application does not by itself establish any safety features in the application. designers must ensure compliance with safety-related requirements and standards applicable to their applications. designer may not use any ti products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). such equipment includes, without limitation, all medical devices identified by the u.s. food and drug administration as class iii devices and equivalent classifications outside the u.s. ti may expressly designate certain products as completing a particular qualification (e.g., q100, military grade, or enhanced product). designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at designers ? own risk. designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. designer will fully indemnify ti and its representatives against any damages, costs, losses, and/or liabilities arising out of designer ? s non- compliance with the terms and provisions of this notice. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2017, texas instruments incorporated

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